2023-11-09 20:19:51 +08:00
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/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _AIC_HAL_QSPI_INTERNAL_H_
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#define _AIC_HAL_QSPI_INTERNAL_H_
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#include <aic_common.h>
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#include <aic_soc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define QSPI_WORK_MODE_SYNC_RX_CPU 0
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#define QSPI_WORK_MODE_SYNC_TX_CPU 1
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#define QSPI_WORK_MODE_ASYNC_RX_CPU 2
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#define QSPI_WORK_MODE_ASYNC_TX_CPU 3
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#define QSPI_WORK_MODE_ASYNC_RX_DMA 4
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#define QSPI_WORK_MODE_ASYNC_TX_DMA 5
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#define HAL_QSPI_STATUS_INTERNAL_MSK (0xFFFFUL << 16)
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#define HAL_QSPI_STATUS_ASYNC_TDONE (0x1UL << 16)
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#define HAL_QSPI_STATUS_ASYNC_DMA_DONE (0x1UL << 17)
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#define HAL_QSPI_STATUS_ASYNC_ALL_DONE (HAL_QSPI_STATUS_ASYNC_TDONE | HAL_QSPI_STATUS_ASYNC_DMA_DONE)
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#define QSPI_IS_ASYNC_ALL_DONE(sts, msk) ((sts & msk) == msk)
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#define PTR2U32(p) ((u32)(unsigned long)(p))
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2024-06-04 19:00:30 +08:00
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#define QSPI_TRANSFER_DATA_LEN_1M 0x100000
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#define QSPI_CPU_DMA_MIN_SPEED_MS (0x800000 >> 10)
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2023-11-09 20:19:51 +08:00
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void show_freq(char *msg, u32 id, u32 hz);
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void hal_qspi_fifo_reset(u32 base, u32 fifo);
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void hal_qspi_show_ists(u32 id, u32 sts);
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int qspi_fifo_write_data(u32 base, u8 *data, u32 len, u32 tmo);
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int qspi_fifo_read_data(u32 base, u8 *data, u32 len, u32 tmo_us);
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int qspi_wait_transfer_done(u32 base, u32 tmo);
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2024-06-04 19:00:30 +08:00
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u32 qspi_calc_timeout(u32 bus_hz, u32 len);
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2023-11-09 20:19:51 +08:00
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#ifdef __cplusplus
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}
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#endif
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#endif
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