2023-08-30 16:21:18 +08:00
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/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Li Siyao <siyao.li@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_PSADC_H_
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#define _ARTINCHIP_HAL_PSADC_H_
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#include "aic_osal.h"
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#define AIC_PSADC_FIFO1_NUM_BITS 20
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#define AIC_PSADC_FIFO2_NUM_BITS 12
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#define AIC_PSADC_TIMEOUT 1000 /* 1000 ms */
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enum aic_psadc_mode {
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AIC_PSADC_MODE_SINGLE = 0,
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AIC_PSADC_MODE_PERIOD = 1
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};
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struct aic_psadc_ch {
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u8 id;
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u8 available;
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enum aic_psadc_mode mode;
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u8 fifo_depth;
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aicos_sem_t complete;
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};
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2024-01-27 08:47:24 +08:00
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void hal_psadc_enable(int enable);
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void hal_psadc_single_queue_mode(int enable);
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void hal_psadc_qc_irq_enable(int enable);
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int hal_psadc_ch_init(struct aic_psadc_ch *chan, u32 pclk);
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irqreturn_t hal_psadc_isr(int irq, void *arg);
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int hal_psadc_read(struct aic_psadc_ch *chan, u32 *val, u32 timeout);
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2023-08-30 16:21:18 +08:00
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struct aic_psadc_ch *hal_psadc_ch_is_valid(u32 ch);
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void hal_psadc_set_ch_num(u32 num);
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2024-01-27 08:47:24 +08:00
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void hal_psadc_status_show(struct aic_psadc_ch *chan);
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2023-08-30 16:21:18 +08:00
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#endif
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