2023-08-30 16:21:18 +08:00
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/*
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2024-09-03 11:16:08 +08:00
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* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
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2023-08-30 16:21:18 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __AIC_HAL_GPIO_H__
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#define __AIC_HAL_GPIO_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "aic_common.h"
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#include "aic_gpio_id.h"
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/* drive-strength */
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#define PIN_DRV_33V_180_OHM 0
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#define PIN_DRV_33V_90_OHM 1
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#define PIN_DRV_33V_60_OHM 2
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#define PIN_DRV_33V_45_OHM 3
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#define PIN_DRV_33V_36_OHM 4
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#define PIN_DRV_33V_30_OHM 5
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#define PIN_DRV_33V_26_OHM 6
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#define PIN_DRV_33V_23_OHM 7
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#define PIN_DRV_18V_300_OHM 0
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#define PIN_DRV_18V_150_OHM 1
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#define PIN_DRV_18V_100_OHM 2
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#define PIN_DRV_18V_75_OHM 3
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#define PIN_DRV_18V_60_OHM 4
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#define PIN_DRV_18V_50_OHM 5
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#define PIN_DRV_18V_43_OHM 6
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#define PIN_DRV_18V_38_OHM 7
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/* bias-pull-down/up */
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#define PIN_PULL_DIS 0
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#define PIN_PULL_DOWN 2
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#define PIN_PULL_UP 3
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/* irq type */
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#define PIN_IRQ_MODE_EDGE_FALLING 0
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#define PIN_IRQ_MODE_EDGE_RISING 1
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#define PIN_IRQ_MODE_LEVEL_LOW 2
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#define PIN_IRQ_MODE_LEVEL_HIGH 3
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#define PIN_IRQ_MODE_EDGE_BOTH 4
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2024-04-03 16:40:57 +08:00
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enum gpio_check_pincfg_type {
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GPIO_CHECK_PIN_FUN = 0,
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GPIO_CHECK_PIN_GEN_OE = 1,
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GPIO_CHECK_PIN_GEN_IE = 2,
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GPIO_CHECK_GEN_IRQ_MODE = 3,
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GPIO_CHECK_PIN_GEN_PIN_DRV = 4,
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GPIO_CHECK_PIN_GEN_PULL = 5
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};
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2023-08-30 16:21:18 +08:00
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#define GPIO_GROUP_SIZE 32
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#define GPIO_GROUP(pin_name) ((pin_name) / GPIO_GROUP_SIZE)
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#define GPIO_GROUP_PIN(pin_name) ((pin_name) % GPIO_GROUP_SIZE)
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#define GPIO_PIN_NAME(_g, _offset) (((_g) * GPIO_GROUP_SIZE) + (_offset))
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struct gpio_cfg {
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uint8_t port;
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uint8_t pin;
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uint8_t func;
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uint8_t pull;
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uint8_t driver;
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};
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#define AIC_PINMUX_BASE(port, pin, func, up, drv) \
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{port - 'A', pin, func, up, drv}
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#define AIC_PINMUX(port, pin, func) \
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AIC_PINMUX_BASE(port, pin, func, PIN_PULL_DIS, 3)
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#define AIC_PINMUX_UP(port, pin, func) \
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AIC_PINMUX_BASE(port, pin, func, PIN_PULL_UP, 3)
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#define AIC_PINMUX_DOWN(port, pin, func) \
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AIC_PINMUX_BASE(port, pin, func, PIN_PULL_DOWN, 3)
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unsigned int hal_gpio_name2pin(const char *name);
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int hal_gpio_get_value(unsigned int group, unsigned int pin,
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unsigned int *pvalue);
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int hal_gpio_set_value(unsigned int group, unsigned int pin,
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unsigned int value);
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int hal_gpio_clr_output(unsigned int group, unsigned int pin);
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int hal_gpio_set_output(unsigned int group, unsigned int pin);
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int hal_gpio_toggle_output(unsigned int group, unsigned int pin);
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int hal_gpio_enable_irq(unsigned int group, unsigned int pin);
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int hal_gpio_disable_irq(unsigned int group, unsigned int pin);
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int hal_gpio_group_get_irq_en(unsigned int group, unsigned int *pen);
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2024-09-03 11:16:08 +08:00
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int hal_gpio_group_set_irq_en(unsigned int group, unsigned int en);
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2023-08-30 16:21:18 +08:00
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int hal_gpio_group_get_irq_stat(unsigned int group, unsigned int *pstat);
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int hal_gpio_group_set_irq_stat(unsigned int group, unsigned int stat);
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int hal_gpio_get_irq_stat(unsigned int group, unsigned int pin,
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unsigned int *pstat);
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int hal_gpio_clr_irq_stat(unsigned int group, unsigned int pin);
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int hal_gpio_set_func(unsigned int group, unsigned int pin, unsigned int func);
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int hal_gpio_get_func(unsigned int group, unsigned int pin,
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unsigned int *pfunc);
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int hal_gpio_set_drive_strength(unsigned int group, unsigned int pin,
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unsigned int strength);
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int hal_gpio_set_bias_pull(unsigned int group, unsigned int pin,
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unsigned int pull);
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int hal_gpio_set_irq_mode(unsigned int group, unsigned int pin,
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unsigned int irq_mode);
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int hal_gpio_direction_input(unsigned int group, unsigned int pin);
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int hal_gpio_direction_output(unsigned int group, unsigned int pin);
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int hal_gpio_set_debounce(unsigned int group, unsigned int pin,
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unsigned int debounce);
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int hal_gpio_cfg(struct gpio_cfg *cfg, u32 cnt);
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2024-04-03 16:40:57 +08:00
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int hal_gpio_get_pincfg(unsigned int group, unsigned int pin, int check_type);
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2024-06-04 19:00:30 +08:00
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int hal_gpio_get_outcfg(unsigned int group, unsigned int pin,
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unsigned int *pvalue);
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2023-08-30 16:21:18 +08:00
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AIC_HAL_GPIO_H__ */
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