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59 lines
1.8 KiB
C
59 lines
1.8 KiB
C
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/*
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* Copyright (c) 2024, ArtInChip Technology CO.,LTD. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Chen JunLong <junlong.chen@artinchip.com>
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*/
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#ifndef _AIC_HAL_DCE_H_
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#define _AIC_HAL_DCE_H_
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#include <aic_common.h>
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#include <aic_soc.h>
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#define DCE_CTL_REG (DCE_BASE + 0x000)
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#define DCE_CFG_REG (DCE_BASE + 0x004)
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#define DCE_IRQ_REG (DCE_BASE + 0x008)
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#define DCE_ISR_REG (DCE_BASE + 0x00C)
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#define DCE_ADDR_REG (DCE_BASE + 0x010)
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#define DCE_LEN_REG (DCE_BASE + 0x014)
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#define DCE_RST_REG (DCE_BASE + 0x040)
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#define DCE_CRC_CFG_REG (DCE_BASE + 0x080)
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#define DCE_CRC_INIT_REG (DCE_BASE + 0x084)
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#define DCE_CRC_XOROUT_REG (DCE_BASE + 0x088)
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#define DCE_CRC_RST_REG (DCE_BASE + 0x0C0)
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#define DCE_SUM_RST_REG (DCE_BASE + 0x140)
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#define DCE_GET_VERSION_REG (DCE_BASE + 0xFFC)
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#define DCE_WAIT_CNT 10000
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#define DCE_CALC_OK 0
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#define DCE_CALC_ERR -1
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#define DCE_CALC_TMO -2
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#define DCE_ALG_CRC 0x1
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#define DCE_ALG_SUM 0x2
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#define DCE_ERR_ALL_MSK 0x07000000
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#define DCE_CRC_FINISH_MSK 0x01
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#define DCE_SUM_FINISH_MSK 0x02
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#define OUTPUT_BIT_IN_WORD_REV (0x1 << 0)
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#define INPUT_BIT_IN_BYTE_REV (0x1 << 1)
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#define INPUT_BIT_IN_WORD_REV (0x1 << 2)
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#define INPUT_BYTE_IN_WORD_REV (0x1 << 3)
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int hal_dce_init(void);
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void hal_dce_deinit(void);
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void hal_dce_checksum_start(u8 *data, u32 len);
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u32 hal_dce_checksum_wait(void);
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u32 hal_dce_checksum_result(void);
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void hal_dce_crc32_cfg(u32 out_bit_in_word, u32 input_bit_in_byte,
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u32 input_bit_in_word, u32 input_byte_in_word);
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void hal_dce_crc32_xor_val(u32 val);
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void hal_dce_crc32_start(u32 crc, u8 *data, u32 len);
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int hal_dce_crc32_wait(void);
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u32 hal_dce_crc32_result(void);
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u32 hal_get_version(void);
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#endif
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