2023-08-30 16:21:18 +08:00
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/*
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2024-09-03 11:16:08 +08:00
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* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
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2023-08-30 16:21:18 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_GPAI_H_
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#define _ARTINCHIP_HAL_GPAI_H_
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#include "aic_osal.h"
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2024-06-04 19:00:30 +08:00
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#define AIC_GPAI_NUM_BITS 12
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#define AIC_GPAI_TIMEOUT 1000 /* 1000 ms */
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#define AIC_GPAI_FIFO_MAX_DEPTH 32
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2023-08-30 16:21:18 +08:00
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enum aic_gpai_mode {
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AIC_GPAI_MODE_SINGLE = 0,
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AIC_GPAI_MODE_PERIOD = 1
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};
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2023-11-30 19:48:02 +08:00
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enum aic_gpai_obtain_data_mode {
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2024-01-27 08:47:24 +08:00
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AIC_GPAI_OBTAIN_DATA_BY_CPU = 1,
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AIC_GPAI_OBTAIN_DATA_BY_DMA = 2,
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AIC_GPAI_OBTAIN_DATA_BY_DO = 3
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2023-11-30 19:48:02 +08:00
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};
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typedef void (*dma_callback)(void *dma_param);
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2024-06-04 19:00:30 +08:00
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typedef void (*irq_callback)(void *cb_param);
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2023-11-30 19:48:02 +08:00
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struct aic_dma_transfer_info
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{
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u32 chan_id;
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struct aic_dma_chan *dma_chan;
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void *buf;
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int buf_size;
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void *callback_param;
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dma_callback callback;
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};
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2024-06-04 19:00:30 +08:00
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struct aic_gpai_irq_info
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{
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u32 chan_id;
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void *callback_param;
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irq_callback callback;
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};
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struct aic_gpai_ch_info
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{
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u32 chan_id;
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u16 adc_values[AIC_GPAI_FIFO_MAX_DEPTH];
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u8 fifo_valid_cnt;
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enum aic_gpai_mode mode;
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};
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2023-08-30 16:21:18 +08:00
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struct aic_gpai_ch {
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u8 id;
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u8 available;
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2024-04-03 16:40:57 +08:00
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u8 adc_acq;
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2023-08-30 16:21:18 +08:00
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enum aic_gpai_mode mode;
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2023-11-30 19:48:02 +08:00
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enum aic_gpai_obtain_data_mode obtain_data_mode;
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2023-08-30 16:21:18 +08:00
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u32 smp_period;
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u32 pclk_rate;
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2024-09-03 11:16:08 +08:00
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u16 avg_data;
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2024-06-04 19:00:30 +08:00
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u16 fifo_data[AIC_GPAI_FIFO_MAX_DEPTH];
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u8 fifo_valid_cnt;
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2023-08-30 16:21:18 +08:00
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u8 fifo_depth;
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u8 fifo_thd;
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u8 hla_enable; // high-level alarm
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u8 lla_enable; // low-level alarm
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u16 hla_thd;
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u16 hla_rm_thd;
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u16 lla_thd;
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u16 lla_rm_thd;
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2023-11-09 20:19:51 +08:00
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u8 irq_count;
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2023-11-30 19:48:02 +08:00
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u8 dma_port_id;
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struct aic_dma_transfer_info dma_rx_info;
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2024-06-04 19:00:30 +08:00
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struct aic_gpai_irq_info irq_info;
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2023-11-09 20:19:51 +08:00
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2023-08-30 16:21:18 +08:00
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aicos_sem_t complete;
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};
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void aich_gpai_enable(int enable);
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void aich_gpai_ch_enable(u32 ch, int enable);
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int aich_gpai_ch_init(struct aic_gpai_ch *chan, u32 pclk);
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irqreturn_t aich_gpai_isr(int irq, void *arg);
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2024-06-04 19:00:30 +08:00
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int aich_gpai_read(struct aic_gpai_ch *chan, u16 *val, u32 timeout);
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2023-08-30 16:21:18 +08:00
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s32 aich_gpai_data2vol(u16 data);
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struct aic_gpai_ch *hal_gpai_ch_is_valid(u32 ch);
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void hal_gpai_set_ch_num(u32 num);
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void aich_gpai_status_show(struct aic_gpai_ch *chan);
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s32 hal_gpai_clk_init(void);
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void hal_gpai_clk_get(struct aic_gpai_ch *chan);
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2024-01-27 08:47:24 +08:00
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#if defined(AIC_GPAI_DRV_V20) && defined(AIC_DMA_DRV)
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2023-11-30 19:48:02 +08:00
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void hal_gpai_config_dma(struct aic_gpai_ch *chan);
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void hal_gpai_start_dma(struct aic_gpai_ch *chan);
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#endif
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2023-08-30 16:21:18 +08:00
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#endif // end of _ARTINCHIP_HAL_GPAI_H_
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