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54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
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/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: zrq <ruiqi.zheng@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_PWMCS_H_
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#define _ARTINCHIP_HAL_PWMCS_H_
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#include "aic_common.h"
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#ifdef CONFIG_FPGA_BOARD_ARTINCHIP
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#define QEP_CLK_RATE 24000000 /* 24 MHz */
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#else
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#define QEP_CLK_RATE 200000000 /* 200 MHz */
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#endif
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#define QEP_POS_CMP_INT_FLG BIT(8)
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enum aic_qep_cnt_mode {
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QUADRATURE_COUNT = 0,
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DIR_COUNT,
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INCREMENTAL_COUNT,
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DECREMENT_COUNT,
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CW_CCW_HIGH_COUNT,
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CW_CCW_LOW_COUNT
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};
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enum aic_qep_icap_mode {
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RESERVED = 0,
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QEP_IDX_RISING,
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QEP_IDS_FALLING,
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QEP_IDX_MKR
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};
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struct aic_qep_data {
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u8 id;
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};
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u32 hal_qep_int_stat(u32 ch);
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void hal_qep_clr_int(u32 ch, u32 stat);
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void hal_qep_set_cnt_ep(u32 i, u32 cnt);
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void hal_qep_set_cnt_cmp(u32 i, u32 cnt);
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void hal_qep_config(u32 ch);
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void hal_qep_int_enable(u32 ch, u32 enable);
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void hal_qep_enable(u32 ch, u32 enable);
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int hal_qep_init(void);
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int hal_qep_deinit(void);
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#endif // end of _ARTINCHIP_HAL_PWMCS_H_
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