2023-08-30 16:21:18 +08:00
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/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_SYSCFG_H_
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#define _ARTINCHIP_HAL_SYSCFG_H_
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#include "aic_common.h"
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typedef enum {
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PHY_INTERFACE_MODE_NA,
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PHY_INTERFACE_MODE_INTERNAL,
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PHY_INTERFACE_MODE_MII,
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PHY_INTERFACE_MODE_GMII,
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PHY_INTERFACE_MODE_SGMII,
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PHY_INTERFACE_MODE_TBI,
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PHY_INTERFACE_MODE_REVMII,
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PHY_INTERFACE_MODE_RMII,
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PHY_INTERFACE_MODE_RGMII,
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PHY_INTERFACE_MODE_RGMII_ID,
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PHY_INTERFACE_MODE_RGMII_RXID,
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PHY_INTERFACE_MODE_RGMII_TXID,
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PHY_INTERFACE_MODE_RTBI,
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PHY_INTERFACE_MODE_SMII,
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_XLGMII,
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PHY_INTERFACE_MODE_MOCA,
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PHY_INTERFACE_MODE_QSGMII,
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PHY_INTERFACE_MODE_TRGMII,
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PHY_INTERFACE_MODE_1000BASEX,
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PHY_INTERFACE_MODE_2500BASEX,
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PHY_INTERFACE_MODE_RXAUI,
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PHY_INTERFACE_MODE_XAUI,
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/* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
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PHY_INTERFACE_MODE_10GBASER,
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PHY_INTERFACE_MODE_USXGMII,
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/* 10GBASE-KR - with Clause 73 AN */
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PHY_INTERFACE_MODE_10GKR,
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PHY_INTERFACE_MODE_MAX,
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} phy_interface_t;
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// #define SYSCFG_GMAC_USE_EXTCLK 1
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// #define SYSCFG_GMAC_TX_DELAY 0xC
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// #define SYSCFG_GMAC_RX_DELAY 0xC
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#define SYSCFG_GMAC0_PHY_MODE PHY_INTERFACE_MODE_RMII
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// #define SYSCFG_GMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII
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void syscfg_usb_phy0_sw_host(s32 sw);
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s32 syscfg_fpga_de_clk_sel_by_div(u8 sclk, u8 pixclk);
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void syscfg_fpga_lcd_io_set(u32 val);
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s32 hal_syscfg_probe(void);
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2024-01-27 08:47:24 +08:00
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u32 syscfg_read_ldo_cfg(void);
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2023-08-30 16:21:18 +08:00
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#endif
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