2023-08-30 16:21:18 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 zx.chen The first version
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*/
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#ifndef CPUPORT_H__
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#define CPUPORT_H__
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#include <rtconfig.h>
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#include <aic_arch.h>
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2024-01-27 08:47:24 +08:00
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#define TSPEND_ADDR (CPU_BASE + 0x80100C)
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2023-08-30 16:21:18 +08:00
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/* bytes of register width */
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#ifdef ARCH_RISCV64
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#define DFSTORE fsd
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#define DFLOAD fld
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#define SFSTORE fsw
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#define SFLOAD flw
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#define STORE sd
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#define LOAD ld
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#define REGBYTES 8
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#define SFREGBYTES 4
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#define DFREGBYTES 8
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#else
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#define DFSTORE fsd
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#define DFLOAD fld
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#define SFSTORE fsw
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#define SFLOAD flw
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#define STORE sw
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#define LOAD lw
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#define REGBYTES 4
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#define SFREGBYTES 4
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#define DFREGBYTES 8
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#endif
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#ifdef ARCH_RISCV_FPU
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#ifdef ARCH_RISCV_FPU_D
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#define FSTORE fsd
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#define FLOAD fld
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#define FREGBYTES 8
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#define rv_floatreg_t uint64_t
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#endif
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#ifdef ARCH_RISCV_FPU_S
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#define FSTORE fsw
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#define FLOAD flw
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#define FREGBYTES 4
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#define rv_floatreg_t uint32_t
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#endif
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#endif
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#endif
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