2024-04-03 16:40:57 +08:00
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/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <rtconfig.h>
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#include <cpuport.h>
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/* Enable interrupts when returning from the handler */
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#define MSTATUS_PRV1 0x3880
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.section .bss
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.align 3
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.global g_base_irqstack
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.global g_top_irqstack
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g_base_irqstack:
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.space AIC_INTERRUPTSTACK_SIZE
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g_top_irqstack:
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.align 2
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.globl g_trap_sp
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.type g_trap_sp, object
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g_trap_sp:
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.long 0
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.size g_trap_sp, .-g_trap_sp
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#ifdef KERNEL_BAREMETAL
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.align 3
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.global g_base_normalstack
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.global g_top_normalstack
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g_base_normalstack:
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.space AIC_NORMALSTACK_SIZE
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g_top_normalstack:
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#endif
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irq_nested_level:
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.long 0
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.text
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.align 2
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.global Default_IRQHandler
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.weak Default_IRQHandler
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.type Default_IRQHandler, %function
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Default_IRQHandler:
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#ifdef __riscv_xthead
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ipush
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#else
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.long 0x0040000b
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#endif
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2024-10-30 16:50:31 +08:00
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#if defined(_ENABLE_BACK_TRACE_STACK_) && defined(_NO_OMIT_FRAME_POINT_)
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addi sp,sp,-8
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STORE s0,(sp)
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csrr a0, mepc
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STORE a0, 4(sp)
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addi s0, sp, 8
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#endif
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2024-04-03 16:40:57 +08:00
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#ifdef ARCH_RISCV_FPU
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addi sp, sp, -(20 * FREGBYTES)
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FSTORE ft0, 0 * FREGBYTES(sp)
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FSTORE ft1, 1 * FREGBYTES(sp)
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FSTORE ft2, 2 * FREGBYTES(sp)
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FSTORE ft3, 3 * FREGBYTES(sp)
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FSTORE ft4, 4 * FREGBYTES(sp)
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FSTORE ft5, 5 * FREGBYTES(sp)
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FSTORE ft6, 6 * FREGBYTES(sp)
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FSTORE ft7, 7 * FREGBYTES(sp)
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FSTORE fa0, 8 * FREGBYTES(sp)
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FSTORE fa1, 9 * FREGBYTES(sp)
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FSTORE fa2, 10 * FREGBYTES(sp)
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FSTORE fa3, 11 * FREGBYTES(sp)
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FSTORE fa4, 12 * FREGBYTES(sp)
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FSTORE fa5, 13 * FREGBYTES(sp)
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FSTORE fa6, 14 * FREGBYTES(sp)
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FSTORE fa7, 15 * FREGBYTES(sp)
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FSTORE ft8, 16 * FREGBYTES(sp)
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FSTORE ft9, 17 * FREGBYTES(sp)
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FSTORE ft10, 18 * FREGBYTES(sp)
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FSTORE ft11, 19 * FREGBYTES(sp)
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#endif
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#if defined(KERNEL_RTTHREAD)
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jal rt_interrupt_enter
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#elif defined(KERNEL_FREERTOS)
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jal aicos_irq_enter
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#endif
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/* call isr */
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/* t1 = irq_num */
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csrr t1, mcause
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andi t1, t1, 0x3FF
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slli t1, t1, 2
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/* irq_handler_func(): t2 = g_irqvector[irq_num] */
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la t0, g_irqvector
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add t0, t0, t1
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lw t2, (t0)
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/* para1 : a0 = irq_num */
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mv a0, t1
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srli a0, a0, 2
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/* para2 : a1 = g_irqdata[irq_num] = irq_data */
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la t0, g_irqdata
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add t0, t0, t1
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lw a1, (t0)
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/* g_irqcnt[irq_num]++ */
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la t0, g_irqcnt
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add a3, t0, t1
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lw t0, (a3)
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addi t0, t0, 1
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sw t0, (a3)
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/* call irq_handler_func(irq_num, irq_data) */
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jalr t2
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#if defined(KERNEL_RTTHREAD)
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jal rt_interrupt_leave
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#elif defined(KERNEL_FREERTOS)
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jal aicos_irq_exit
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#endif
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#ifdef ARCH_RISCV_FPU
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FLOAD ft0, 0 * FREGBYTES(sp)
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FLOAD ft1, 1 * FREGBYTES(sp)
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FLOAD ft2, 2 * FREGBYTES(sp)
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FLOAD ft3, 3 * FREGBYTES(sp)
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FLOAD ft4, 4 * FREGBYTES(sp)
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FLOAD ft5, 5 * FREGBYTES(sp)
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FLOAD ft6, 6 * FREGBYTES(sp)
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FLOAD ft7, 7 * FREGBYTES(sp)
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FLOAD fa0, 8 * FREGBYTES(sp)
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FLOAD fa1, 9 * FREGBYTES(sp)
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FLOAD fa2, 10 * FREGBYTES(sp)
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FLOAD fa3, 11 * FREGBYTES(sp)
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FLOAD fa4, 12 * FREGBYTES(sp)
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FLOAD fa5, 13 * FREGBYTES(sp)
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FLOAD fa6, 14 * FREGBYTES(sp)
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FLOAD fa7, 15 * FREGBYTES(sp)
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FLOAD ft8, 16 * FREGBYTES(sp)
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FLOAD ft9, 17 * FREGBYTES(sp)
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FLOAD ft10,18 * FREGBYTES(sp)
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FLOAD ft11,19 * FREGBYTES(sp)
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addi sp, sp, (20 * FREGBYTES)
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#endif
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2024-10-30 16:50:31 +08:00
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#if defined(_ENABLE_BACK_TRACE_STACK_) && defined(_NO_OMIT_FRAME_POINT_)
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lw s0, (sp)
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addi sp, sp, 8
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#endif
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2024-04-03 16:40:57 +08:00
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#ifdef __riscv_xthead
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ipop
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#else
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.long 0x0050000b
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#endif
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/******************************************************************************
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* Functions:
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* void trap(void);
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* default exception handler
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******************************************************************************/
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.align 2
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.global trap
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.type trap, %function
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trap:
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/* Check for interrupt */
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addi sp, sp, -4
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sw t0, 0x0(sp)
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csrr t0, mcause
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blt t0, x0, .Lirq
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addi sp, sp, 4
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2024-10-30 16:50:31 +08:00
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//la t0, g_trap_sp
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mv t0, sp
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2024-04-03 16:40:57 +08:00
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addi t0, t0, -132
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sw x1, 0(t0)
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sw x2, 4(t0)
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sw x3, 8(t0)
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sw x4, 12(t0)
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sw x6, 20(t0)
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sw x7, 24(t0)
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sw x8, 28(t0)
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sw x9, 32(t0)
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sw x10, 36(t0)
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sw x11, 40(t0)
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sw x12, 44(t0)
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sw x13, 48(t0)
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sw x14, 52(t0)
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sw x15, 56(t0)
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sw x16, 60(t0)
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sw x17, 64(t0)
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sw x18, 68(t0)
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sw x19, 72(t0)
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sw x20, 76(t0)
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sw x21, 80(t0)
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sw x22, 84(t0)
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sw x23, 88(t0)
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sw x24, 92(t0)
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sw x25, 96(t0)
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sw x26, 100(t0)
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sw x27, 104(t0)
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sw x28, 108(t0)
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sw x29, 112(t0)
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sw x30, 116(t0)
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sw x31, 120(t0)
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csrr a0, mepc
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sw a0, 124(t0)
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csrr a0, mstatus
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sw a0, 128(t0)
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mv a0, t0
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lw t0, -4(sp)
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mv sp, a0
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sw t0, 16(sp)
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la a5, trap_c
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jalr a5
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2024-10-30 16:50:31 +08:00
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#ifdef KERNEL_RTTHREAD
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mv a0, sp
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addi a0, a0, 132
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csrr a1, mscratch
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csrr a2, mepc
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la a5, print_stack
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jalr a5
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#endif
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#if defined(_ENABLE_BACK_TRACE_STACK_) && defined(KERNEL_RTTHREAD)
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#define CALL_STACK_MAX_DEPTH 32
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la a0, rt_current_thread
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beqz a0, .
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#ifdef _NO_OMIT_FRAME_POINT_
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mv t0, sp
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la t1, CALL_STACK_MAX_DEPTH
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slli t1, t1, 2
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sub t0, t0, t1
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csrr a1, mepc
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STORE a1, (t0)
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mv a1, s0
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li t1, 1
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1:
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// check sram addr
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li t2, 0x30000000
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la t3, AIC_SRAM_TOTAL_SIZE
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add t3, t2, t3
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blt a1, t2, 2f
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bge a1, t3, 2f
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addi a2, a1, -(4)
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blt a2, t2, 2f
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bge a2, t3, 2f
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addi a2, a1, -(8)
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blt a2, t2, 2f
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bge a2, t3, 2f
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j 3f
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2:
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// check psram addr
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li t2, 0x40000000
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la t3, AIC_PSRAM_SIZE
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add t3, t2, t3
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blt a1, t2, 4f
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bge a1, t3, 4f
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addi a2, a1, -(4)
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blt a2, t2, 4f
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bge a2, t3, 4f
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addi a2, a1, -(8)
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blt a2, t2, 4f
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bge a2, t3, 4f
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3:
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// get ra
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LOAD a2, -4(a1)
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slli t2, t1, 2
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add t2, t2, t0
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STORE a2, (t2)
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// get next fp
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LOAD a1, -8(a1)
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//inc call depth
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addi t1, t1, 1
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// check end
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li a2, 0xdeadbeef
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beq a1, a2, 4f
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la a2, CALL_STACK_MAX_DEPTH
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blt t1, a2, 1b
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4:
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mv a0, t1
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mv a1, t0
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mv sp, t0
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la a5, print_back_trace
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jalr a5
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#else
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mv a0, sp
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addi a0, a0, 132
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csrr a1, mscratch
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csrr a2, mepc
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la a5, backtrace_call_stack
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jalr a5
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#endif
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#endif
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j .
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2024-04-03 16:40:57 +08:00
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.Lirq:
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lw t0, 0x0(sp)
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addi sp, sp, 4
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j Default_IRQHandler
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.align 6
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.weak Default_Handler
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.global Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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/* Check for nmi */
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addi sp, sp, -8
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sw t0, 0x0(sp)
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sw t1, 0x4(sp)
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csrr t0, mcause
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andi t0, t0, 0x3FF
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li t1, 24
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beq t0, t1, .NMI_Handler
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lw t0, 0x0(sp)
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lw t1, 0x4(sp)
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addi sp, sp, 8
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j trap
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.NMI_Handler:
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lw t0, 0x0(sp)
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lw t1, 0x4(sp)
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|
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addi sp, sp, 8
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addi sp, sp, -64
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sw ra, 0(sp)
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|
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sw t0, 4(sp)
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sw t1, 8(sp)
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sw t2, 12(sp)
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sw a0, 16(sp)
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sw a1, 20(sp)
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sw a2, 24(sp)
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|
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sw a3, 28(sp)
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|
sw a4, 32(sp)
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sw a5, 36(sp)
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sw a6, 40(sp)
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sw a7, 44(sp)
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|
|
sw t3, 48(sp)
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|
sw t4, 52(sp)
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|
sw t5, 56(sp)
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sw t6, 60(sp)
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|
|
#ifdef ARCH_RISCV_FPU
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|
|
|
addi sp, sp, -(20*FREGBYTES)
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|
|
FSTORE ft0, 0 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft1, 1 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft2, 2 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft3, 3 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft4, 4 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft5, 5 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft6, 6 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft7, 7 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa0, 8 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa1, 9 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa2, 10 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa3, 11 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa4, 12 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa5, 13 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa6, 14 * FREGBYTES(sp)
|
|
|
|
|
FSTORE fa7, 15 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft8, 16 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft9, 17 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft10, 18 * FREGBYTES(sp)
|
|
|
|
|
FSTORE ft11, 19 * FREGBYTES(sp)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
la t0, g_nmivector
|
|
|
|
|
lw t0, (t0)
|
|
|
|
|
jalr t0
|
|
|
|
|
|
|
|
|
|
#ifdef ARCH_RISCV_FPU
|
|
|
|
|
FLOAD ft0, 0 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft1, 1 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft2, 2 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft3, 3 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft4, 4 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft5, 5 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft6, 6 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft7, 7 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa0, 8 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa1, 9 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa2, 10 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa3, 11 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa4, 12 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa5, 13 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa6, 14 * FREGBYTES(sp)
|
|
|
|
|
FLOAD fa7, 15 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft8, 16 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft9, 17 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft10, 18 * FREGBYTES(sp)
|
|
|
|
|
FLOAD ft11, 19 * FREGBYTES(sp)
|
|
|
|
|
|
|
|
|
|
addi sp, sp, (20 * FREGBYTES)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
lw ra, 0(sp)
|
|
|
|
|
lw t0, 4(sp)
|
|
|
|
|
lw t1, 8(sp)
|
|
|
|
|
lw t2, 12(sp)
|
|
|
|
|
lw a0, 16(sp)
|
|
|
|
|
lw a1, 20(sp)
|
|
|
|
|
lw a2, 24(sp)
|
|
|
|
|
lw a3, 28(sp)
|
|
|
|
|
lw a4, 32(sp)
|
|
|
|
|
lw a5, 36(sp)
|
|
|
|
|
lw a6, 40(sp)
|
|
|
|
|
lw a7, 44(sp)
|
|
|
|
|
lw t3, 48(sp)
|
|
|
|
|
lw t4, 52(sp)
|
|
|
|
|
lw t5, 56(sp)
|
|
|
|
|
lw t6, 60(sp)
|
|
|
|
|
|
|
|
|
|
addi sp, sp, 64
|
|
|
|
|
mret
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
.size Default_Handler, . - Default_Handler
|
|
|
|
|
|
|
|
|
|
/* Macro to define default handlers. Default handler
|
|
|
|
|
* will be weak symbol and just dead loops. They can be
|
|
|
|
|
* overwritten by other handlers */
|
|
|
|
|
.macro def_irq_handler handler_name
|
|
|
|
|
.weak \handler_name
|
|
|
|
|
.globl \handler_name
|
|
|
|
|
.set \handler_name, Default_Handler
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
// def_irq_handler PendSV_Handler
|
|
|
|
|
// def_irq_handler SysTick_Handler
|
|
|
|
|
|
|
|
|
|
#ifdef KERNEL_BAREMETAL
|
|
|
|
|
.align 6
|
|
|
|
|
.weak PendSV_Handler
|
|
|
|
|
.global PendSV_Handler
|
|
|
|
|
.type PendSV_Handler, %function
|
|
|
|
|
PendSV_Handler:
|
|
|
|
|
j trap
|
|
|
|
|
|
|
|
|
|
.size PendSV_Handler, . - PendSV_Handler
|
|
|
|
|
#endif
|
