mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-14 18:38:55 +00:00
256 lines
7.6 KiB
JSON
256 lines
7.6 KiB
JSON
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{
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"psram": {
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"cfg0": { //OPI APS3208K 8M PSRAM
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"common": {
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"clock": "198000000",
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"cs0_pins": "0x0",
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"cs1_pins": "0x0",
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"xspi_ctl": "0x116d",
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"xspi_tcr": "0x280011",
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"xspi_cfg": "0x03020001",
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"xspi_ldo": "0x17", //1.92V
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"psram_cfg0": "0x03030303",
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"psram_cfg1": "0x00400001",
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"xspi_cs0_iocfg1": "0x02020202",
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"xspi_cs0_iocfg2": "0x02020202",
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"xspi_cs0_iocfg3": "0x36060503",
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"xspi_cs0_iocfg4": "0x26",
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"xspi_cs1_iocfg1": "0x02020202",
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"xspi_cs1_iocfg2": "0x02020202",
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"xspi_cs1_iocfg3": "0x36060503",
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"xspi_cs1_iocfg4": "0x26",
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},
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"reset": {
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"proto": "0xff000001",
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"buf": "0x00ffffff",
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},
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"getid": {
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"proto": "0x40030204",
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"id": "0x80c980c9",
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"buf": "0xffffffff",
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},
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"init": {
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"proto0": "0xc0000002", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
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"buf0": "0x19000000",
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"proto1": "0xc0000402",
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"buf1": "0x80000000",
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"proto2": "0xffffffff",
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"buf2": "0xffffffff",
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"proto3": "0xffffffff",
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"buf3": "0xffffffff",
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},
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"xip_cfg": {
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"wr_proto": "0x80020002",
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"wr_buf": "0xffffffff",
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"rd_proto": "0x00060003",
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"rd_buf": "0xffffffff",
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},
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"backup": {
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"buf0": "0xAA55AA55", // training_value1
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"buf1": "0x55AA55AA", // training_value2
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"buf2": "0x02080100", //byte0:read_hold (0x02); byte1:write_hold (0x08); byte3:axi_read_first(0x01); byte4: bit mode
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"buf3": "0xFFFFFF04",
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"buf4": "0xFFFFFF05",
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"buf5": "0xFFFFFF06",
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"buf6": "0xFFFFFF07",
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"buf7": "0xFFFFFF08",
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"buf8": "0xFFFFFF09",
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"buf9": "0xFFFFFF00",
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},
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},
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"cfg1": { // XCCELA AP12816 16M PSRAM
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"common": {
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"clock": "198000000",
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"cs0_pins": "0x0",
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"cs1_pins": "0x0",
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"xspi_ctl": "0x116d",
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"xspi_tcr": "0x280011",
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"xspi_cfg": "0x03000001",
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"xspi_ldo": "0x17", //1.92V
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"psram_cfg0": "0x03030304", //cmd_lines, addr_lines, data_lines, addr_width
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"psram_cfg1": "0x02000001",
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"xspi_cs0_iocfg1": "0x02020202",
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"xspi_cs0_iocfg2": "0x02020202",
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"xspi_cs0_iocfg3": "0x36060405",
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"xspi_cs0_iocfg4": "0x26",
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"xspi_cs1_iocfg1": "0x02020202",
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"xspi_cs1_iocfg2": "0x02020202",
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"xspi_cs1_iocfg3": "0x36060403",
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"xspi_cs1_iocfg4": "0x26",
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},
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"reset": {
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"proto": "0xff000001",
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"buf": "0x00ffffff",
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},
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"getid": {
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"proto": "0x40040104",
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"id": "0xdd8ddd8d",
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"buf": "0xffffffff",
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},
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"init": {
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"proto0": "0xc0000001", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
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"buf0": "0x11000000",
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"proto1": "0xc0000401",
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"buf1": "0x20000000",
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"proto2": "0xc0000801",
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"buf2": "0x4c000000",
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"proto3": "0xffffffff",
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"buf3": "0xffffffff",
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},
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"xip_cfg": {
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"wr_proto": "0x80070002", //cmd: byte[0]=0x80; dummy: byte[1]=0x07; addr: byte[2]=0x08; len: byte[3]=0x02;
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"wr_buf": "0xffffffff",
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"rd_proto": "0x00070003",
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"rd_buf": "0xffffffff",
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},
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"backup": {
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"buf0": "0x5555aaaa",
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"buf1": "0xaaaa5555",
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"buf2": "0x05050101", //byte0:read_hold; byte1:write_hold; byte3:axi_read_first; byte4:bit mode
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"buf3": "0xFFFFFF04",
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"buf4": "0xFFFFFF05",
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"buf5": "0xFFFFFF06",
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"buf6": "0xFFFFFF07",
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"buf7": "0xFFFFFF08",
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"buf8": "0xFFFFFF09",
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"buf9": "0xFFFFFF00",
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},
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},
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"cfg2": { // XCCELA UnilC SCKW18X12816 16M PSRAM
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"common": {
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"clock": "198000000",
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"cs0_pins": "0x0",
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"cs1_pins": "0x0",
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"xspi_ctl": "0x116d",
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"xspi_tcr": "0x280011",
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"xspi_cfg": "0x03000001",
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"xspi_ldo": "0x17", //1.92V
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"psram_cfg0": "0x03030304", //cmd_lines, addr_lines, data_lines, addr_width
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"psram_cfg1": "0x02000001",
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"xspi_cs0_iocfg1": "0x02020202",
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"xspi_cs0_iocfg2": "0x02020202",
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"xspi_cs0_iocfg3": "0x36060405",
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"xspi_cs0_iocfg4": "0x26",
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"xspi_cs1_iocfg1": "0x02020202",
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"xspi_cs1_iocfg2": "0x02020202",
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"xspi_cs1_iocfg3": "0x36060403",
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"xspi_cs1_iocfg4": "0x26",
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},
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"reset": {
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"proto": "0xff000001",
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"buf": "0x00ffffff",
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},
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"getid": {
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"proto": "0x40040104",
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"id": "0xc59ac59a",
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"buf": "0xffffffff",
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},
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"init": {
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"proto0": "0xc0000001", //cmd: byte[0]=0xc0; dummy: byte[1]=0x00; addr: byte[2]=0x00; len: byte[3]=0x02;
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"buf0": "0x10000000",
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"proto1": "0xc0000401",
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"buf1": "0x20000000",
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"proto2": "0xc0000801",
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"buf2": "0x4c000000",
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"proto3": "0xffffffff",
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"buf3": "0xffffffff",
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},
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"xip_cfg": {
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"wr_proto": "0x80070002", //cmd: byte[0]=0x80; dummy: byte[1]=0x07; addr: byte[2]=0x08; len: byte[3]=0x02;
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"wr_buf": "0xffffffff",
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"rd_proto": "0x00070003",
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"rd_buf": "0xffffffff",
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},
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"backup": {
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"buf0": "0x5555aaaa",
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"buf1": "0xaaaa5555",
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"buf2": "0x05050101", //byte0:read_hold; byte1:write_hold; byte3:axi_read_first; byte4:bit mode
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"buf3": "0xFFFFFF04",
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"buf4": "0xFFFFFF05",
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"buf5": "0xFFFFFF06",
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"buf6": "0xFFFFFF07",
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"buf7": "0xFFFFFF08",
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"buf8": "0xFFFFFF09",
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"buf9": "0xFFFFFF00",
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},
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},
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},
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"system": {
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"upgmode": { // Set PIN to enter BROM's upgrading mode
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// If set upgmode_pin_cfg_reg to "0", disable bootpin detect in PBP
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"upgmode_pin_cfg_reg": "0x18700080", // PINMUX REG, PA0
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"upgmode_pin_cfg_val": "0x10321", // PINMUX VAL
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"upgmode_pin_input_reg": "0x18700000", // INPUT VAL REG
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"upgmode_pin_input_msk": "0x1", // Bit MSK
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"upgmode_pin_input_val": "0x0", // Bit VAL
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"upgmode_pin_pullup_dly": "500", // us
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},
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"uart": { // PBP's uart setting, remove uart setting to disable log in PBP
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"main": {
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//"uart_id": "0", // UART0 for log output
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//"uart_tx_pin_cfg_reg": "0x18700080", // PA0
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//"uart_tx_pin_cfg_val": "0x035",
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//"uart_rx_pin_cfg_reg": "0x18700084", // PA1
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//"uart_rx_pin_cfg_val": "0x035",
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// "uart_id": "0", // UART0 for log output
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// "uart_tx_pin_cfg_reg": "0x18700E88", // PN2
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// "uart_tx_pin_cfg_val": "0x324",
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// "uart_rx_pin_cfg_reg": "0x18700E8C", // PN3
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// "uart_rx_pin_cfg_val": "0x324",
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"uart_id": "1", // UART1 for log output
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"uart_tx_pin_cfg_reg": "0x18700088", // PA2
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"uart_tx_pin_cfg_val": "0x325",
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"uart_rx_pin_cfg_reg": "0x1870008C", // PA3
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"uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "1", // UART1 for log output
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// "uart_tx_pin_cfg_reg": "0x18700090", // PA4
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x18700094", // PA5
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// "uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "3", // UART3 for log output
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// "uart_tx_pin_cfg_reg": "0x187004B8", // PE14
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x187004BC", // PE15
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// "uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "4", // UART4 for log output
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// "uart_tx_pin_cfg_reg": "0x18700198", // PB6
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x1870019C", // PB7
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// "uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "5", // UART5 for log output
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// "uart_tx_pin_cfg_reg": "0x18700490", // PE4
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x18700494", // PE5
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// "uart_rx_pin_cfg_val": "0x325",
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},
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},
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"jtag": {
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"jtag_only": "0", // 1: Boot code stop in PBP after DDR init and jtag init
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"main": {
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"jtag_id": "0",
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"jtag_ms_pin_cfg_reg": "0x187000A8", // PA10
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"jtag_ms_pin_cfg_val": "0x338",
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"jtag_ck_pin_cfg_reg": "0x187000AC", // PA11
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"jtag_ck_pin_cfg_val": "0x338",
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// "jtag_ms_pin_cfg_reg": "0x18700280", // PC0
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// "jtag_ms_pin_cfg_val": "0x338",
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// "jtag_ck_pin_cfg_reg": "0x18700294", // PC5
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// "jtag_ck_pin_cfg_val": "0x338",
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},
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},
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},
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}
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