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optimize dcache prefech and aic_build.py

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刘可亮
2023-11-14 15:35:32 +08:00
parent aaa66c7b20
commit 07d3226dd2
3 changed files with 5 additions and 5 deletions
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8
bsp/artinchip/sys/d13x/include/core_rv32.h
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@@ -1051,11 +1051,11 @@ __STATIC_INLINE void csi_dcache_enable (void)
__DCACHE_IALL(); /* invalidate all dcache */
cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */
__set_MHCR(cache);
mhint = __get_MHINT();
mhint &= ~(MHINT_DPLD_Msk | MHINT_AMR_Msk | MHINT_PREF_N_Msk);
mhint |= (1<<MHINT_DPLD_Pos) | (1<<MHINT_AMR_Pos) | (3<<MHINT_PREF_N_Pos);
__set_MHINT(mhint);
}
mhint = __get_MHINT();
mhint &= ~(MHINT_DPLD_Msk | MHINT_AMR_Msk | MHINT_PREF_N_Msk);
mhint |= (1<<MHINT_AMR_Pos);
__set_MHINT(mhint);
__DSB();
__ISB();
#endif