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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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V1.0.5
This commit is contained in:
刘可亮
@@ -5,53 +5,394 @@
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*
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* Authors: Geo <guojun.dong@artinchip.com>
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*/
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#include <stdint.h>
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#include <sys_freq.h>
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#include <rtconfig.h>
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#include <rtdef.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <aic_core.h>
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#include <aic_soc.h>
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#include <aic_arch.h>
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#include <aic_common.h>
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#include <aic_io.h>
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#include <aic_errno.h>
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#include <aic_list.h>
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#include <aic_osal.h>
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#include <drivers/i2c.h>
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#include <aic_hal_gpio.h>
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#include <hal_i2c.h>
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#ifndef AIC_DEV_I2C0_10BIT
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#define AIC_DEV_I2C0_10BIT 0
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#endif
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#ifndef AIC_DEV_I2C1_10BIT
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#define AIC_DEV_I2C1_10BIT 0
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#endif
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#ifndef AIC_DEV_I2C2_10BIT
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#define AIC_DEV_I2C2_10BIT 0
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#endif
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#ifndef AIC_DEV_I2C3_10BIT
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#define AIC_DEV_I2C3_10BIT 0
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#endif
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#ifndef AIC_DEV_I2C4_10BIT
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#define AIC_DEV_I2C4_10BIT 0
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#endif
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#ifndef AIC_DEV_SP_I2C_10BIT
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#define AIC_DEV_SP_I2C_10BIT 0
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#endif
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#ifndef AIC_DEV_I2C0_100K_SPEED
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#define AIC_DEV_I2C0_100K_SPEED 0
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#endif
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#ifndef AIC_DEV_I2C1_100K_SPEED
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#define AIC_DEV_I2C1_100K_SPEED 0
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#endif
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#ifndef AIC_DEV_I2C2_100K_SPEED
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#define AIC_DEV_I2C2_100K_SPEED 0
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#endif
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#ifndef AIC_DEV_I2C3_100K_SPEED
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#define AIC_DEV_I2C3_100K_SPEED 0
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#endif
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#ifndef AIC_DEV_I2C4_100K_SPEED
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#define AIC_DEV_I2C4_100K_SPEED 0
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#endif
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#ifndef AIC_DEV_SP_I2C_100K_SPEED
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#define AIC_DEV_SP_I2C_100K_SPEED 0
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#endif
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#ifndef AIC_DEV_I2C0_SLAVE_MODE
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#define AIC_DEV_I2C0_SLAVE_MODE 0
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#endif
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#ifndef AIC_DEV_I2C1_SLAVE_MODE
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#define AIC_DEV_I2C1_SLAVE_MODE 0
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#endif
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#ifndef AIC_DEV_I2C2_SLAVE_MODE
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#define AIC_DEV_I2C2_SLAVE_MODE 0
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#endif
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#ifndef AIC_DEV_I2C3_SLAVE_MODE
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#define AIC_DEV_I2C3_SLAVE_MODE 0
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#endif
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#ifndef AIC_DEV_I2C4_SLAVE_MODE
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#define AIC_DEV_I2C4_SLAVE_MODE 0
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#endif
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#ifndef AIC_DEV_SP_I2C_SLAVE_MODE
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#define AIC_DEV_SP_I2C_SLAVE_MODE 0
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#endif
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#ifndef AIC_DEV_I2C0_SLAVE_ADDR
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#define AIC_DEV_I2C0_SLAVE_ADDR 0
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#endif
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#ifndef AIC_DEV_I2C1_SLAVE_ADDR
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#define AIC_DEV_I2C1_SLAVE_ADDR 0
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#endif
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#ifndef AIC_DEV_I2C2_SLAVE_ADDR
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#define AIC_DEV_I2C2_SLAVE_ADDR 0
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#endif
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#ifndef AIC_DEV_I2C3_SLAVE_ADDR
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#define AIC_DEV_I2C3_SLAVE_ADDR 0
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#endif
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#ifndef AIC_DEV_I2C4_SLAVE_ADDR
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#define AIC_DEV_I2C4_SLAVE_ADDR 0
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#endif
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#ifndef AIC_DEV_SP_I2C_SLAVE_ADDR
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#define AIC_DEV_SP_I2C_SLAVE_ADDR 0
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#endif
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struct aic_i2c_bus {
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struct rt_i2c_bus_device bus;
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uint8_t index;
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uint32_t reg_base;
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char *device_name;
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aic_i2c_ctrl aic_bus;
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struct rt_completion cmd_complete;
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};
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static struct aic_i2c_bus g_aic_i2c_dev[AIC_I2C_CH_NUM];
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irqreturn_t aic_i2c_slave_irqhandler(int irq, void * data)
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{
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int index = irq - I2C0_IRQn;
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uint32_t intr_stat;
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uint8_t val;
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uint8_t fifo_num;
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struct slave_param parm;
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aic_i2c_ctrl *i2c_dev;
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i2c_dev = &g_aic_i2c_dev[index].aic_bus;
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intr_stat = hal_i2c_get_raw_interrupt_state(i2c_dev);
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fifo_num = hal_i2c_get_receive_fifo_num(i2c_dev);
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if (!i2c_dev->slave.slave_cb)
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{
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/*
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* if the slave is not registered, we need to read the fifo empty
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* to avoid interrupts from being triggered continuously
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*/
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for (int i = 0; i < fifo_num; i++)
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hal_i2c_get_receive_data(i2c_dev);
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hal_i2c_clear_all_irq_flags(i2c_dev);
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pr_debug("slave callback not register!\n");
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return IRQ_NONE;
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}
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if (intr_stat & I2C_INTR_START_DET) {
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parm.cmd = I2C_SLAVE_WRITE_REQUESTED;
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parm.arg = &val;
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i2c_dev->slave.slave_cb((void *)&parm);
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hal_i2c_clear_irq_flags(i2c_dev, I2C_INTR_START_DET);
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}
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if (intr_stat & I2C_INTR_RX_FULL) {
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val = hal_i2c_get_receive_data(i2c_dev);
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parm.cmd = I2C_SLAVE_WRITE_RECEIVED;
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parm.arg = &val;
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if (!i2c_dev->slave.slave_cb((void *)&parm)) {
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pr_debug("Byte 0x%02x acked!\n", val);
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}
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hal_i2c_clear_irq_flags(i2c_dev, I2C_INTR_RX_FULL);
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}
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if (intr_stat & I2C_INTR_RD_REQ) {
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parm.cmd = I2C_SLAVE_READ_REQUESTED;
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parm.arg = &val;
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i2c_dev->slave.slave_cb((void *)&parm);
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hal_i2c_transmit_data(i2c_dev, *parm.arg);
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parm.cmd = I2C_SLAVE_READ_PROCESSED;
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parm.arg = &val;
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i2c_dev->slave.slave_cb((void *)&parm);
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hal_i2c_clear_irq_flags(i2c_dev, I2C_INTR_RD_REQ);
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}
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if (intr_stat & I2C_INTR_RX_DONE) {
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parm.cmd = I2C_SLAVE_STOP;
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parm.arg = &val;
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i2c_dev->slave.slave_cb((void *)&parm);
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hal_i2c_clear_irq_flags(i2c_dev, I2C_INTR_RX_DONE);
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}
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if (intr_stat & I2C_INTR_RX_UNDER) {
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hal_i2c_clear_irq_flags(i2c_dev, I2C_INTR_RX_UNDER);
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}
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if (intr_stat & I2C_INTR_TX_ABRT) {
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hal_i2c_clear_irq_flags(i2c_dev, I2C_INTR_TX_ABRT);
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}
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return IRQ_HANDLED;
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}
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#ifdef AIC_I2C_INTERRUPT_MODE
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static void aic_i2c_handle_read(struct aic_i2c_ctrl *i2c_dev)
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{
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struct aic_i2c_msg *msg = i2c_dev->msg;
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int rx_valid;
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uint32_t idx;
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idx = i2c_dev->index;
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rx_valid = hal_i2c_get_receive_fifo_num(i2c_dev);
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while (rx_valid--) {
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msg->buf[i2c_dev->buf_read_idx++] = hal_i2c_get_receive_data(i2c_dev);
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}
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/* message transfer done if it is a read message */
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if (i2c_dev->buf_read_idx == msg->len) {
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hal_i2c_disable_all_irq(i2c_dev);
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rt_completion_done(&g_aic_i2c_dev[idx].cmd_complete);
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}
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}
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static void aic_i2c_handle_write(struct aic_i2c_ctrl *i2c_dev)
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{
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struct aic_i2c_msg *msg = i2c_dev->msg;
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int rx_valid, tx_valid, buf_len;
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uint32_t intr_mask = I2C_INTR_MASTER_MASK;
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uint32_t idx;
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idx = i2c_dev->index;
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if ((i2c_dev->msg_status == MSG_IDLE) && (msg->len == 0)
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&& (i2c_dev->is_first_message) && (i2c_dev->is_last_message)) {
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uint32_t cmd = 0;
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cmd |= I2C_DATA_CMD_STOP;
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/* Write operation */
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hal_i2c_transmit_data_with_cmd(i2c_dev, cmd);
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hal_i2c_disable_all_irq(i2c_dev);
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rt_completion_done(&g_aic_i2c_dev[idx].cmd_complete);
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}
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i2c_dev->msg_status = MSG_IN_PROCESS;
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rx_valid = I2C_FIFO_DEPTH - hal_i2c_get_receive_fifo_num(i2c_dev);
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tx_valid = I2C_FIFO_DEPTH - hal_i2c_get_transmit_fifo_num(i2c_dev);
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buf_len = msg->len - i2c_dev->buf_write_idx;
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while (buf_len > 0 && rx_valid > 0 && tx_valid > 0) {
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uint32_t cmd = 0;
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if (buf_len == 1 && i2c_dev->is_last_message) {
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cmd |= I2C_DATA_CMD_STOP;
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}
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if (!i2c_dev->is_first_message && !i2c_dev->buf_write_idx) {
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cmd |= I2C_DATA_CMD_RESTART;
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}
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if (msg->flags & RT_I2C_RD) {
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cmd |= I2C_DATA_CMD_READ;
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hal_i2c_transmit_data_with_cmd(i2c_dev, cmd);
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rx_valid--;
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} else {
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hal_i2c_transmit_data_with_cmd(i2c_dev, cmd | msg->buf[i2c_dev->buf_write_idx]);
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/* ensure the data is sent out */
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while (hal_i2c_get_transmit_fifo_num(i2c_dev) != 0) {};
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}
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i2c_dev->buf_write_idx++;
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tx_valid--;
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buf_len--;
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if (i2c_dev->buf_write_idx == msg->len) {
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intr_mask &= ~I2C_INTR_TX_EMPTY;
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hal_i2c_flags_mask(i2c_dev, intr_mask);
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/* message transfer done if it is a write message */
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if (!(msg->flags & RT_I2C_RD)) {
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hal_i2c_disable_all_irq(i2c_dev);
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rt_completion_done(&g_aic_i2c_dev[idx].cmd_complete);
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}
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}
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}
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}
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irqreturn_t aic_i2c_irqhandler(int irq, void * data)
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{
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int index = irq - I2C0_IRQn;
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uint32_t status = 0;
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aic_i2c_ctrl *i2c_dev;
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i2c_dev = &g_aic_i2c_dev[index].aic_bus;
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status = hal_i2c_get_raw_interrupt_state(i2c_dev);
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/* clear all interrupt flags */
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hal_i2c_clear_all_irq_flags(i2c_dev);
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if (status & I2C_INTR_TX_ABRT) {
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i2c_dev->msg_err = -I2C_INTR_ERROR_ABRT;
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goto i2c_err;
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}
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if (status & I2C_INTR_RX_UNDER) {
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i2c_dev->msg_err = -I2C_INTR_ERROR_RX;
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goto i2c_err;
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}
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if (status & I2C_INTR_RX_FULL) {
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aic_i2c_handle_read(i2c_dev);
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}
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if (status & I2C_INTR_TX_EMPTY) {
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aic_i2c_handle_write(i2c_dev);
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}
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i2c_err:
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if (status & (I2C_INTR_TX_ABRT | I2C_INTR_RX_UNDER | I2C_INTR_STOP_DET)) {
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hal_i2c_disable_all_irq(i2c_dev);
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rt_completion_done(&g_aic_i2c_dev[index].cmd_complete);
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}
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return IRQ_HANDLED;
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}
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static void aic_i2c_xfer_msg_init(struct aic_i2c_ctrl *i2c_dev)
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{
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i2c_dev->buf_write_idx = 0;
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i2c_dev->buf_read_idx = 0;
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i2c_dev->msg_err = 0;
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i2c_dev->abort_source = 0;
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i2c_dev->msg_status = MSG_IDLE;
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/* clear and enable interrupts */
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hal_i2c_clear_all_irq_flags(i2c_dev);
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hal_i2c_master_enable_irq(i2c_dev);
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}
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static int aic_i2c_xfer_msg(struct aic_i2c_ctrl *i2c_dev, struct aic_i2c_msg *msg,
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bool is_first, bool is_last)
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{
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int ret = 0;
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rt_err_t timeout;
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uint32_t idx;
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i2c_dev->msg = msg;
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i2c_dev->is_first_message = is_first;
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i2c_dev->is_last_message = is_last;
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idx = i2c_dev->index;
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rt_completion_init(&g_aic_i2c_dev[idx].cmd_complete);
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if (is_first) {
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/* Set the slave address */
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hal_i2c_target_addr(i2c_dev, msg->addr);
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/* Enable i2c dev */
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hal_i2c_module_enable(i2c_dev);
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ret = hal_i2c_wait_bus_free(i2c_dev, 10);
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if (ret)
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return ret;
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}
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aic_i2c_xfer_msg_init(i2c_dev);
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timeout = rt_completion_wait(&g_aic_i2c_dev[idx].cmd_complete, 1000);
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if (timeout) {
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pr_err("message xfer timeout\n");
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ret = I2C_TIMEOUT;
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}
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if (i2c_dev->msg_err) {
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ret = I2C_ERR;
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}
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return ret;
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}
|
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static rt_size_t aic_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[], rt_uint32_t num)
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{
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CHECK_PARAM(bus, -EINVAL);
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|
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aic_i2c_ctrl *i2c_dev;
|
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int ret = 0, index;
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uint8_t idx;
|
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|
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idx = bus->parent.device_id;
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i2c_dev = &g_aic_i2c_dev[idx].aic_bus;
|
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|
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for (index = 0; index < num; index++) {
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i2c_dev->msg = (struct aic_i2c_msg*)msgs;
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ret = aic_i2c_xfer_msg(i2c_dev, &i2c_dev->msg[index], index == 0, index == (num-1));
|
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}
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hal_i2c_module_disable(i2c_dev);
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|
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return (ret < 0) ? ret : num;
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}
|
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#else
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static rt_size_t aic_i2c_master_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[], rt_uint32_t num)
|
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{
|
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CHECK_PARAM(bus, -EINVAL);
|
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|
||||
struct aic_i2c_bus *i2c_bus = (struct aic_i2c_bus *)bus;
|
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struct rt_i2c_msg *msg = NULL;
|
||||
aic_i2c_ctrl *i2c_dev;
|
||||
int ret_msg_len = 0;
|
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int32_t bytes_cnt = 0;
|
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int8_t is_last_message = 0;
|
||||
uint8_t index;
|
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|
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for (uint32_t index = 0; index < num; index++) {
|
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msg = &msgs[index];
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if (index == num -1)
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index = bus->parent.device_id;
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i2c_dev = &g_aic_i2c_dev[index].aic_bus;
|
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|
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for (uint32_t i = 0; i < num; i++) {
|
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msg = &msgs[i];
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if (i == num -1)
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is_last_message = 1;
|
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else
|
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is_last_message = 0;
|
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|
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if ((msg->flags & RT_I2C_RD)) {
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||||
bytes_cnt = aic_i2c_master_receive_msg(i2c_bus->reg_base, (struct aic_i2c_msg*)msg, is_last_message);
|
||||
bytes_cnt = hal_i2c_master_receive_msg(i2c_dev,
|
||||
(struct aic_i2c_msg*)msg, is_last_message);
|
||||
} else {
|
||||
bytes_cnt = aic_i2c_master_send_msg(i2c_bus->reg_base, (struct aic_i2c_msg*)msg, is_last_message);
|
||||
bytes_cnt = hal_i2c_master_send_msg(i2c_dev,
|
||||
(struct aic_i2c_msg*)msg, is_last_message);
|
||||
}
|
||||
|
||||
if (bytes_cnt == msg->len) {
|
||||
@@ -61,18 +402,40 @@ static rt_size_t aic_i2c_master_xfer(struct rt_i2c_bus_device *bus,
|
||||
|
||||
return ret_msg_len;
|
||||
}
|
||||
#endif
|
||||
|
||||
static rt_err_t aic_i2c_slave_control(struct rt_i2c_bus_device *bus,
|
||||
rt_uint32_t cmd, void *arg)
|
||||
{
|
||||
RT_ASSERT(bus != RT_NULL);
|
||||
|
||||
aic_i2c_ctrl *i2c_dev;
|
||||
|
||||
uint8_t index = bus->parent.device_id;
|
||||
i2c_dev = &g_aic_i2c_dev[index].aic_bus;
|
||||
|
||||
struct aic_i2c_slave_info *slave_info = (struct aic_i2c_slave_info *)arg;
|
||||
|
||||
i2c_dev->slave.slave_cb = slave_info->slave_cb;
|
||||
i2c_dev->slave.callback_param = slave_info->callback_param;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t aic_i2c_bus_control(struct rt_i2c_bus_device *bus,
|
||||
rt_uint32_t cmd, rt_uint32_t value)
|
||||
{
|
||||
RT_ASSERT(bus != RT_NULL);
|
||||
|
||||
struct aic_i2c_bus *i2c_bus = (struct aic_i2c_bus *)bus;
|
||||
aic_i2c_ctrl *i2c_dev;
|
||||
|
||||
uint8_t index = bus->parent.device_id;
|
||||
i2c_dev = &g_aic_i2c_dev[index].aic_bus;
|
||||
|
||||
switch(cmd)
|
||||
{
|
||||
case RT_I2C_DEV_CTRL_CLK:
|
||||
aic_i2c_speed_mode_select(i2c_bus->reg_base, I2C_DEFALT_CLOCK, value);
|
||||
hal_i2c_speed_mode_select(i2c_dev, I2C_DEFALT_CLOCK, value);
|
||||
break;
|
||||
default:
|
||||
return -RT_EIO;
|
||||
@@ -83,62 +446,99 @@ static rt_err_t aic_i2c_bus_control(struct rt_i2c_bus_device *bus,
|
||||
|
||||
const struct rt_i2c_bus_device_ops i2c_ops = {
|
||||
aic_i2c_master_xfer,
|
||||
RT_NULL, // slave
|
||||
aic_i2c_bus_control, // bus control
|
||||
RT_NULL,
|
||||
aic_i2c_bus_control,
|
||||
aic_i2c_slave_control,
|
||||
};
|
||||
|
||||
static struct aic_i2c_bus aic_i2c_list[] = {
|
||||
static struct aic_i2c_bus aic_i2c_dev[] = {
|
||||
#ifdef AIC_USING_I2C0
|
||||
{
|
||||
.index = 0,
|
||||
.reg_base = I2C0_BASE,
|
||||
.device_name = "i2c0",
|
||||
.bus.ops = &i2c_ops,
|
||||
.aic_bus = {
|
||||
.index = 0,
|
||||
.reg_base = I2C0_BASE,
|
||||
.device_name = "i2c0",
|
||||
.addr_bit = AIC_DEV_I2C0_10BIT,
|
||||
.speed_mode = AIC_DEV_I2C0_100K_SPEED,
|
||||
.bus_mode = AIC_DEV_I2C0_SLAVE_MODE,
|
||||
.slave_addr = AIC_DEV_I2C0_SLAVE_ADDR,
|
||||
},
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef AIC_USING_I2C1
|
||||
{
|
||||
.index = 1,
|
||||
.reg_base = I2C1_BASE,
|
||||
.device_name = "i2c1",
|
||||
.bus.ops = &i2c_ops,
|
||||
.aic_bus = {
|
||||
.index = 1,
|
||||
.reg_base = I2C1_BASE,
|
||||
.device_name = "i2c1",
|
||||
.addr_bit = AIC_DEV_I2C1_10BIT,
|
||||
.speed_mode = AIC_DEV_I2C1_100K_SPEED,
|
||||
.bus_mode = AIC_DEV_I2C1_SLAVE_MODE,
|
||||
.slave_addr = AIC_DEV_I2C1_SLAVE_ADDR,
|
||||
},
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef AIC_USING_I2C2
|
||||
{
|
||||
.index = 2,
|
||||
.reg_base = I2C2_BASE,
|
||||
.device_name = "i2c2",
|
||||
.bus.ops = &i2c_ops,
|
||||
.aic_bus = {
|
||||
.index = 2,
|
||||
.reg_base = I2C2_BASE,
|
||||
.device_name = "i2c2",
|
||||
.addr_bit = AIC_DEV_I2C2_10BIT,
|
||||
.speed_mode = AIC_DEV_I2C2_100K_SPEED,
|
||||
.bus_mode = AIC_DEV_I2C2_SLAVE_MODE,
|
||||
.slave_addr = AIC_DEV_I2C2_SLAVE_ADDR,
|
||||
},
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef AIC_USING_I2C3
|
||||
{
|
||||
.index = 3,
|
||||
.reg_base = I2C3_BASE,
|
||||
.device_name = "i2c3",
|
||||
.bus.ops = &i2c_ops,
|
||||
.aic_bus = {
|
||||
.index = 3,
|
||||
.reg_base = I2C3_BASE,
|
||||
.device_name = "i2c3",
|
||||
.addr_bit = AIC_DEV_I2C3_10BIT,
|
||||
.speed_mode = AIC_DEV_I2C3_100K_SPEED,
|
||||
.bus_mode = AIC_DEV_I2C3_SLAVE_MODE,
|
||||
.slave_addr = AIC_DEV_I2C3_SLAVE_ADDR,
|
||||
},
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef AIC_USING_I2C4
|
||||
{
|
||||
.index = 4,
|
||||
.reg_base = I2C4_BASE,
|
||||
.device_name = "i2c4",
|
||||
.bus.ops = &i2c_ops,
|
||||
.aic_bus = {
|
||||
.index = 4,
|
||||
.reg_base = I2C4_BASE,
|
||||
.device_name = "i2c4",
|
||||
.addr_bit = AIC_DEV_I2C4_10BIT,
|
||||
.speed_mode = AIC_DEV_I2C4_100K_SPEED,
|
||||
.bus_mode = AIC_DEV_I2C4_SLAVE_MODE,
|
||||
.slave_addr = AIC_DEV_I2C4_SLAVE_ADDR,
|
||||
},
|
||||
},
|
||||
#endif
|
||||
|
||||
#ifdef AIC_USING_SP_I2C
|
||||
{
|
||||
.index = 5,
|
||||
.reg_base = SP_I2C_BASE,
|
||||
.device_name = "sp_i2c",
|
||||
.bus.ops = &i2c_ops,
|
||||
.aic_bus = {
|
||||
.index = 5,
|
||||
.reg_base = SP_I2C_BASE,
|
||||
.device_name = "sp_i2c",
|
||||
.addr_bit = AIC_DEV_SP_I2C_10BIT,
|
||||
.speed_mode = AIC_DEV_SP_I2C_100K_SPEED,
|
||||
.bus_mode = AIC_DEV_SP_I2C_SLAVE_MODE,
|
||||
.slave_addr = AIC_DEV_SP_I2C_SLAVE_ADDR,
|
||||
},
|
||||
},
|
||||
#endif
|
||||
};
|
||||
@@ -146,29 +546,27 @@ static struct aic_i2c_bus aic_i2c_list[] = {
|
||||
static int aic_hw_i2c_register()
|
||||
{
|
||||
int ret = -1;
|
||||
uint8_t index;
|
||||
|
||||
for (uint8_t i = 0; i < ARRAY_SIZE(aic_i2c_list); i++) {
|
||||
ret = aic_i2c_init(aic_i2c_list[i].index);
|
||||
for (uint8_t i = 0; i < ARRAY_SIZE(aic_i2c_dev); i++) {
|
||||
index = aic_i2c_dev[i].aic_bus.index;
|
||||
aic_i2c_dev[i].bus.parent.device_id = index;
|
||||
g_aic_i2c_dev[index] = aic_i2c_dev[i];
|
||||
|
||||
ret = hal_i2c_init(&aic_i2c_dev[i].aic_bus);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = aic_i2c_set_master_slave_mode(aic_i2c_list[i].reg_base, true);
|
||||
if (ret) {
|
||||
return ret;
|
||||
#ifdef AIC_I2C_INTERRUPT_MODE
|
||||
aicos_request_irq(I2C0_IRQn + index, aic_i2c_irqhandler, 0, "i2c", NULL);
|
||||
#endif
|
||||
if (aic_i2c_dev[i].aic_bus.bus_mode) {
|
||||
aicos_request_irq(I2C0_IRQn + index, aic_i2c_slave_irqhandler, 0, "i2c_slave", NULL);
|
||||
}
|
||||
|
||||
hal_i2c_set_hold(aic_i2c_list[i].reg_base, 10);
|
||||
aic_i2c_master_10bit_addr(aic_i2c_list[i].reg_base, false);
|
||||
aic_i2c_slave_10bit_addr(aic_i2c_list[i].reg_base, false);
|
||||
|
||||
aic_i2c_master_enable_transmit_irq(aic_i2c_list[i].reg_base);
|
||||
aic_i2c_master_enable_receive_irq(aic_i2c_list[i].reg_base);
|
||||
|
||||
aic_i2c_speed_mode_select(aic_i2c_list[i].reg_base, I2C_DEFALT_CLOCK, true);
|
||||
|
||||
ret = rt_i2c_bus_device_register(&aic_i2c_list[i].bus,
|
||||
aic_i2c_list[i].device_name);
|
||||
ret = rt_i2c_bus_device_register(&aic_i2c_dev[i].bus,
|
||||
aic_i2c_dev[i].aic_bus.device_name);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user