wen/luban-lite-t3e-pro
1
0
Fork 0
mirror of https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git synced 2025-12-15 19:08:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

V1.0.5

Browse Source
This commit is contained in:
刘可亮
2024-06-04 19:00:30 +08:00
parent 990c72f5be
commit 0a13af6a1d
1668 changed files with 342810 additions and 37726 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
packages/third-party/lwip/contrib/ports/drv/aic/Kconfig.dev vendored
View File

@@ -34,11 +34,13 @@ menu "gmac0 parameter"
int "gmac0 rx delay"
default 0
range 0 31
depends on AIC_DEV_GMAC0_RGMII
config AIC_DEV_GMAC0_TXDELAY
int "gmac0 tx delay"
default 0
range 0 31
depends on AIC_DEV_GMAC0_RGMII
config AIC_DEV_GMAC0_IPADDR
string "gmac0 ip addr"
@@ -52,9 +54,15 @@ menu "gmac0 parameter"
string "gmac0 netmask"
default "255.255.255.0"
config AIC_DEV_GMAC0_USE_CHIPID
bool "gmac0 mac address use chip-id"
default y
select AIC_USING_SID
config AIC_DEV_GMAC0_MACADDR
string "gmac0 mac addr"
default "002244887766"
depends on !AIC_DEV_GMAC0_USE_CHIPID
config AIC_DEV_GMAC0_PHYADDR
int "gmac0 phy mdio addr"
@@ -95,15 +103,35 @@ menu "gmac1 parameter"
int "gmac1 rx delay"
default 0
range 0 31
depends on AIC_DEV_GMAC1_RGMII
config AIC_DEV_GMAC1_TXDELAY
int "gmac1 tx delay"
default 0
range 0 31
depends on AIC_DEV_GMAC1_RGMII
config AIC_DEV_GMAC1_IPADDR
string "gmac1 ip addr"
default "192.168.3.21"
config AIC_DEV_GMAC1_GW
string "gmac1 gateway addr"
default "192.168.3.1"
config AIC_DEV_GMAC1_NETMASK
string "gmac1 netmask"
default "255.255.255.0"
config AIC_DEV_GMAC1_USE_CHIPID
bool "gmac1 mac address use chip-id"
default y
select AIC_USING_SID
config AIC_DEV_GMAC1_MACADDR
string "gmac1 mac addr"
default "003344557799"
default "001133557788"
depends on !AIC_DEV_GMAC1_USE_CHIPID
config AIC_DEV_GMAC1_PHYADDR
int "gmac1 phy mdio addr"

14
packages/third-party/lwip/contrib/ports/drv/aic/aic_mac.c vendored
View File

@@ -158,7 +158,7 @@ int aicmac_init(uint32_t port)
/* Check the parameters */
assert_param(port < MAX_ETH_MAC_PORT);
memset(dctl, 0, sizeof(dctl));
memset(&dctl[port], 0, sizeof(dctl[0]));
/* HW Low-Level Init */
aicmac_low_level_init(port, ENABLE);
@@ -167,9 +167,9 @@ int aicmac_init(uint32_t port)
aicmac_sw_reset(port);
/* Wait for software reset */
while (aicmac_get_sw_reset_status(port) == SET) {
}
/* phy reset must after mac reset */
if (mac_config[port].phyrst_gpio_name) {
pin = hal_gpio_name2pin(mac_config[port].phyrst_gpio_name);
@@ -239,6 +239,11 @@ int aicmac_init(uint32_t port)
writel(tmpreg, MAC(port, macrxfunc));
/* (4) macfrmflt */
#if LWIP_IPV6
tmpreg = readl(MAC(port, macfrmflt));
tmpreg |= 0x80000001;
writel(tmpreg, MAC(port, macfrmflt));
#endif
/* (5) flowctl */
tmpreg = readl(MAC(port, flowctl));
@@ -624,7 +629,7 @@ void aicmac_dma_tx_desc_init(uint32_t port)
/* Set Second Address Chained bit */
pdesc->control = ETH_DMATxDesc_TCH;
#ifdef LWIP_PTP
pdesc->control |= ETH_DMATxDesc_TTSE;
#endif
@@ -648,6 +653,7 @@ void aicmac_dma_tx_desc_init(uint32_t port)
pdesc->buff2_addr = (uint32_t)(unsigned long)txdesc_tbl;
}
}
/* after write: flush cache */
aicmac_dcache_clean((uintptr_t)txdesc_tbl, sizeof(aicmac_dma_desc_t) * count);

2
packages/third-party/lwip/contrib/ports/drv/aic/aic_mac.h vendored
View File

@@ -61,6 +61,8 @@ typedef struct {
typedef struct {
struct netif netif;
uint32_t port;
aicos_mutex_t eth_tx_mutex;
aicos_event_t eth_rx_event;
}aicmac_netif_t;
/* default config */

247
packages/third-party/lwip/contrib/ports/drv/aic/aic_phy.c vendored
View File

@@ -1,4 +1,5 @@
/*
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
@@ -20,69 +21,69 @@
static const struct phy_setting settings[] = {
#if 0
/* 400G */
PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseDR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseSR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseCR4_Full ),
PHY_SETTING( 400000, FULL, 400000baseKR4_Full ),
PHY_SETTING( 400000, FULL, 400000baseLR4_ER4_FR4_Full ),
PHY_SETTING( 400000, FULL, 400000baseDR4_Full ),
PHY_SETTING( 400000, FULL, 400000baseSR4_Full ),
/* 200G */
PHY_SETTING( 200000, FULL, 200000baseCR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseKR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseLR4_ER4_FR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseDR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseSR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseCR2_Full ),
PHY_SETTING( 200000, FULL, 200000baseKR2_Full ),
PHY_SETTING( 200000, FULL, 200000baseLR2_ER2_FR2_Full ),
PHY_SETTING( 200000, FULL, 200000baseDR2_Full ),
PHY_SETTING( 200000, FULL, 200000baseSR2_Full ),
/* 100G */
PHY_SETTING( 100000, FULL, 100000baseCR4_Full ),
PHY_SETTING( 100000, FULL, 100000baseKR4_Full ),
PHY_SETTING( 100000, FULL, 100000baseLR4_ER4_Full ),
PHY_SETTING( 100000, FULL, 100000baseSR4_Full ),
PHY_SETTING( 100000, FULL, 100000baseCR2_Full ),
PHY_SETTING( 100000, FULL, 100000baseKR2_Full ),
PHY_SETTING( 100000, FULL, 100000baseLR2_ER2_FR2_Full ),
PHY_SETTING( 100000, FULL, 100000baseDR2_Full ),
PHY_SETTING( 100000, FULL, 100000baseSR2_Full ),
PHY_SETTING( 100000, FULL, 100000baseCR_Full ),
PHY_SETTING( 100000, FULL, 100000baseKR_Full ),
PHY_SETTING( 100000, FULL, 100000baseLR_ER_FR_Full ),
PHY_SETTING( 100000, FULL, 100000baseDR_Full ),
PHY_SETTING( 100000, FULL, 100000baseSR_Full ),
/* 56G */
PHY_SETTING( 56000, FULL, 56000baseCR4_Full ),
PHY_SETTING( 56000, FULL, 56000baseKR4_Full ),
PHY_SETTING( 56000, FULL, 56000baseLR4_Full ),
PHY_SETTING( 56000, FULL, 56000baseSR4_Full ),
/* 50G */
PHY_SETTING( 50000, FULL, 50000baseCR2_Full ),
PHY_SETTING( 50000, FULL, 50000baseKR2_Full ),
PHY_SETTING( 50000, FULL, 50000baseSR2_Full ),
PHY_SETTING( 50000, FULL, 50000baseCR_Full ),
PHY_SETTING( 50000, FULL, 50000baseKR_Full ),
PHY_SETTING( 50000, FULL, 50000baseLR_ER_FR_Full ),
PHY_SETTING( 50000, FULL, 50000baseDR_Full ),
PHY_SETTING( 50000, FULL, 50000baseSR_Full ),
/* 40G */
PHY_SETTING( 40000, FULL, 40000baseCR4_Full ),
PHY_SETTING( 40000, FULL, 40000baseKR4_Full ),
PHY_SETTING( 40000, FULL, 40000baseLR4_Full ),
PHY_SETTING( 40000, FULL, 40000baseSR4_Full ),
/* 25G */
PHY_SETTING( 25000, FULL, 25000baseCR_Full ),
PHY_SETTING( 25000, FULL, 25000baseKR_Full ),
PHY_SETTING( 25000, FULL, 25000baseSR_Full ),
/* 20G */
PHY_SETTING( 20000, FULL, 20000baseKR2_Full ),
PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ),
/* 400G */
PHY_SETTING(400000, FULL, 400000baseCR8_Full),
PHY_SETTING(400000, FULL, 400000baseKR8_Full),
PHY_SETTING(400000, FULL, 400000baseLR8_ER8_FR8_Full),
PHY_SETTING(400000, FULL, 400000baseDR8_Full),
PHY_SETTING(400000, FULL, 400000baseSR8_Full),
PHY_SETTING(400000, FULL, 400000baseCR4_Full),
PHY_SETTING(400000, FULL, 400000baseKR4_Full),
PHY_SETTING(400000, FULL, 400000baseLR4_ER4_FR4_Full),
PHY_SETTING(400000, FULL, 400000baseDR4_Full),
PHY_SETTING(400000, FULL, 400000baseSR4_Full),
/* 200G */
PHY_SETTING(200000, FULL, 200000baseCR4_Full),
PHY_SETTING(200000, FULL, 200000baseKR4_Full),
PHY_SETTING(200000, FULL, 200000baseLR4_ER4_FR4_Full),
PHY_SETTING(200000, FULL, 200000baseDR4_Full),
PHY_SETTING(200000, FULL, 200000baseSR4_Full),
PHY_SETTING(200000, FULL, 200000baseCR2_Full),
PHY_SETTING(200000, FULL, 200000baseKR2_Full),
PHY_SETTING(200000, FULL, 200000baseLR2_ER2_FR2_Full),
PHY_SETTING(200000, FULL, 200000baseDR2_Full),
PHY_SETTING(200000, FULL, 200000baseSR2_Full),
/* 100G */
PHY_SETTING(100000, FULL, 100000baseCR4_Full),
PHY_SETTING(100000, FULL, 100000baseKR4_Full),
PHY_SETTING(100000, FULL, 100000baseLR4_ER4_Full),
PHY_SETTING(100000, FULL, 100000baseSR4_Full),
PHY_SETTING(100000, FULL, 100000baseCR2_Full),
PHY_SETTING(100000, FULL, 100000baseKR2_Full),
PHY_SETTING(100000, FULL, 100000baseLR2_ER2_FR2_Full),
PHY_SETTING(100000, FULL, 100000baseDR2_Full),
PHY_SETTING(100000, FULL, 100000baseSR2_Full),
PHY_SETTING(100000, FULL, 100000baseCR_Full),
PHY_SETTING(100000, FULL, 100000baseKR_Full),
PHY_SETTING(100000, FULL, 100000baseLR_ER_FR_Full),
PHY_SETTING(100000, FULL, 100000baseDR_Full),
PHY_SETTING(100000, FULL, 100000baseSR_Full),
/* 56G */
PHY_SETTING(56000, FULL, 56000baseCR4_Full),
PHY_SETTING(56000, FULL, 56000baseKR4_Full),
PHY_SETTING(56000, FULL, 56000baseLR4_Full),
PHY_SETTING(56000, FULL, 56000baseSR4_Full),
/* 50G */
PHY_SETTING(50000, FULL, 50000baseCR2_Full),
PHY_SETTING(50000, FULL, 50000baseKR2_Full),
PHY_SETTING(50000, FULL, 50000baseSR2_Full),
PHY_SETTING(50000, FULL, 50000baseCR_Full),
PHY_SETTING(50000, FULL, 50000baseKR_Full),
PHY_SETTING(50000, FULL, 50000baseLR_ER_FR_Full),
PHY_SETTING(50000, FULL, 50000baseDR_Full),
PHY_SETTING(50000, FULL, 50000baseSR_Full),
/* 40G */
PHY_SETTING(40000, FULL, 40000baseCR4_Full),
PHY_SETTING(40000, FULL, 40000baseKR4_Full),
PHY_SETTING(40000, FULL, 40000baseLR4_Full),
PHY_SETTING(40000, FULL, 40000baseSR4_Full),
/* 25G */
PHY_SETTING(25000, FULL, 25000baseCR_Full),
PHY_SETTING(25000, FULL, 25000baseKR_Full),
PHY_SETTING(25000, FULL, 25000baseSR_Full),
/* 20G */
PHY_SETTING(20000, FULL, 20000baseKR2_Full),
PHY_SETTING(20000, FULL, 20000baseMLD2_Full),
/* 10G */
PHY_SETTING(10000, FULL, 10000baseCR_Full),
PHY_SETTING(10000, FULL, 10000baseER_Full),
@@ -281,9 +282,9 @@ int aicphy_read_abilities(uint32_t port)
int err = 0;
/*
linkmode_set_bit_array(phy_basic_ports_array,
ARRAY_SIZE(phy_basic_ports_array),
phydev->supported);
linkmode_set_bit_array(phy_basic_ports_array,
ARRAY_SIZE(phy_basic_ports_array),
phydev->supported);
*/
//linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported, 1);
linkmode_mod_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported, 1);
@@ -342,7 +343,7 @@ int aicphy_config_advert(uint32_t port)
/* Only allow advertising what this PHY supports */
/* linkmode_and(phydev->advertising, phydev->advertising,
phydev->supported);*/
phydev->supported);*/
phydev->advertising[0] = phydev->supported[0];
adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
@@ -360,9 +361,9 @@ int aicphy_config_advert(uint32_t port)
return ETH_ERROR;
/* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
* 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
* logical 1.
*/
* 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
* logical 1.
*/
if (!(bmsr & BMSR_ESTATEN))
return ETH_SUCCESS;
@@ -549,8 +550,8 @@ int aicphy_update_link(uint32_t port)
return ETH_ERROR;
/* Autoneg is being started, therefore disregard BMSR value and
* report link as down.
*/
* report link as down.
*/
if (bmcr & BMCR_ANRESTART)
goto done;
@@ -563,8 +564,8 @@ done:
phydev->autoneg_complete = status & BMSR_ANEGCOMPLETE ? 1 : 0;
/* Consider the case that autoneg was started and "aneg complete"
* bit has been reset, but "link up" bit not yet.
*/
* bit has been reset, but "link up" bit not yet.
*/
if (phydev->autoneg && !phydev->autoneg_complete)
phydev->link = 0;
@@ -606,75 +607,76 @@ int aicphy_read_status(uint32_t port)
return ETH_SUCCESS;
}
void aic_phy_poll(void)
void aic_phy_poll(struct netif *netif)
{
uint32_t port = aic_netif.port;
struct netif *netif = &aic_netif.netif;
aicmac_netif_t *aic_netif = (aicmac_netif_t *)netif;
uint32_t port = aic_netif->port;
aic_phy_device_t *phydev = &phy_device[port];
static int old_link = 0;
int err;
/* Pool phy satus */
err = aicphy_read_status(port);
if (err){
pr_err("%s fail.\n", __func__);
return ;
}
/* Pool phy satus */
err = aicphy_read_status(port);
if (err) {
pr_err("%s fail.\n", __func__);
return;
}
/* Phy link status not change */
if (old_link == phydev->link)
return ;
old_link = phydev->link;
/* Phy link status not change */
if (old_link == phydev->link)
return;
old_link = phydev->link;
/* Phy link status change: DOWN -> UP */
if (phydev->link){
pr_info(" Port %d link UP! %s mode: speed %dM, %s duplex, flow control %s.\n",
(int)port,
(phydev->autoneg ? "autoneg" : "fixed"),
phydev->speed,
(phydev->duplex ? "full" : "half"),
(phydev->pause ? "on" : "off"));
/* Phy link status change: DOWN -> UP */
if (phydev->link) {
pr_info(" Port %d link UP! %s mode: speed %dM, %s duplex, flow control %s.\n",
(int)port,
(phydev->autoneg ? "autoneg" : "fixed"),
phydev->speed,
(phydev->duplex ? "full" : "half"),
(phydev->pause ? "on" : "off"));
/* Config mac base on autoneg result */
if (phydev->autoneg){
aicmac_set_mac_speed(port, phydev->speed);
aicmac_set_mac_duplex(port, phydev->duplex);
aicmac_set_mac_pause(port, phydev->pause);
}
/* Config mac base on autoneg result */
if (phydev->autoneg) {
aicmac_set_mac_speed(port, phydev->speed);
aicmac_set_mac_duplex(port, phydev->duplex);
aicmac_set_mac_pause(port, phydev->pause);
}
/* Enable MAC and DMA transmission and reception */
aicmac_start(port);
/* Enable MAC and DMA transmission and reception */
aicmac_start(port);
/* Netif set phy linkup */
netif_set_link_up(netif);
/* Netif set phy linkup */
netif_set_link_up(netif);
/* Phy link status change: UP -> DOWN */
} else {
pr_info(" Port %d link DOWN!\n", (int)port);
/* Phy link status change: UP -> DOWN */
} else {
pr_info(" Port %d link DOWN!\n", (int)port);
/* Disable MAC and DMA transmission and reception */
aicmac_stop(port);
/* Disable MAC and DMA transmission and reception */
aicmac_stop(port);
/* Netif set phy linkdown */
netif_set_link_down(netif);
}
/* Netif set phy linkdown */
netif_set_link_down(netif);
}
}
void aicphy_poll_thread(void *pvParameters)
{
uint32_t port = aic_netif.port;
struct netif *netif = &aic_netif.netif;
aicmac_netif_t *aic_netif = (aicmac_netif_t *)pvParameters;
uint32_t port = aic_netif->port;
struct netif *netif = &aic_netif->netif;
aic_phy_device_t *phydev = &phy_device[port];
int old_link = 0;
int err;
while(1){
while(1) {
/* Sleep */
aicos_msleep(PHY_POLL_TASK_INTERVAL_MS);
/* Pool phy satus */
err = aicphy_read_status(port);
if (err){
if (err) {
pr_err("%s fail.\n", __func__);
continue;
}
@@ -685,7 +687,7 @@ void aicphy_poll_thread(void *pvParameters)
old_link = phydev->link;
/* Phy link status change: DOWN -> UP */
if (phydev->link){
if (phydev->link) {
pr_info(" Port %d link UP! %s mode: speed %dM, %s duplex, flow control %s.\n",
(int)port,
(phydev->autoneg ? "autoneg" : "fixed"),
@@ -694,7 +696,7 @@ void aicphy_poll_thread(void *pvParameters)
(phydev->pause ? "on" : "off"));
/* Config mac base on autoneg result */
if (phydev->autoneg){
if (phydev->autoneg) {
aicmac_set_mac_speed(port, phydev->speed);
aicmac_set_mac_duplex(port, phydev->duplex);
aicmac_set_mac_pause(port, phydev->pause);
@@ -719,8 +721,9 @@ void aicphy_poll_thread(void *pvParameters)
}
}
int aicphy_init(uint32_t port)
int aicphy_init(aicmac_netif_t *aic_netif)
{
uint32_t port = aic_netif->port;
aicmac_config_t *config = &mac_config[port];
aic_phy_device_t *phydev = &phy_device[port];
phydev->autoneg = config->autonegotiation;
@@ -743,7 +746,7 @@ int aicphy_init(uint32_t port)
#if !NO_SYS
/* create the task that handles the ETH_MAC */
aicos_thread_create("eth_phy_poll", PHY_POLL_TASK_STACK_SIZE,
PHY_POLL_TASK_PRIORITY, aicphy_poll_thread, NULL);
PHY_POLL_TASK_PRIORITY, aicphy_poll_thread, aic_netif);
#endif
return ETH_SUCCESS;
}

15
packages/third-party/lwip/contrib/ports/drv/aic/aic_phy.h vendored
View File

@@ -1,4 +1,5 @@
/*
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
@@ -68,10 +69,10 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_25000baseCR_Full_BIT = 31,
/* Last allowed bit for __ETHTOOL_LINK_MODE_LEGACY_MASK is bit
* 31. Please do NOT define any SUPPORTED_* or ADVERTISED_*
* macro for bits > 31. The only way to use indices > 31 is to
* use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
*/
* 31. Please do NOT define any SUPPORTED_* or ADVERTISED_*
* macro for bits > 31. The only way to use indices > 31 is to
* use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
*/
ETHTOOL_LINK_MODE_25000baseKR_Full_BIT = 32,
ETHTOOL_LINK_MODE_25000baseSR_Full_BIT = 33,
@@ -329,8 +330,8 @@ enum ethtool_link_mode_bit_indices {
#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
int aicphy_init(uint32_t port);
void aic_phy_poll(void);
int aicphy_init(aicmac_netif_t *aic_netif);
void aic_phy_poll(struct netif *netif);
#ifdef __cplusplus
}
#endif

77
packages/third-party/lwip/contrib/ports/drv/aic/aicmac_macaddr.c vendored Normal file
View File

@@ -0,0 +1,77 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "aicmac_macaddr.h"
#include "hal_efuse.h"
#include "aic_log.h"
#include <string.h>
#define AICMAC_CHIPID_LENGTH 6
static int aicmac_efuse_read(u32 addr, void *data, u32 size)
{
u32 wid, wval, rest, cnt;
u8 *pd, *pw;
int ret;
if (hal_efuse_wait_ready()) {
pr_err("eFuse is not ready.\n");
return -1;
}
pd = data;
rest = size;
while (rest > 0) {
wid = addr >> 2;
ret = hal_efuse_read(wid, &wval);
if (ret)
break;
pw = (u8 *)&wval;
cnt = rest;
if (addr % 4) {
if (rest > (4 - (addr % 4)))
cnt = (4 - (addr % 4));
memcpy(pd, pw + (addr % 4), cnt);
} else {
if (rest > 4)
cnt = 4;
memcpy(pd, pw, cnt);
}
pd += cnt;
addr += cnt;
rest -= cnt;
}
return (int)(size - rest);
}
static inline int aicmac_get_chipid(unsigned char out_chipid[AICMAC_CHIPID_LENGTH])
{
return aicmac_efuse_read(0x10, out_chipid, AICMAC_CHIPID_LENGTH);
}
void aicmac_get_macaddr_from_chipid(int port, unsigned char out_addr[6])
{
unsigned char chipid[AICMAC_CHIPID_LENGTH];
unsigned char key[AICMAC_CHIPID_LENGTH] = {'a', 'i', 'c', 'k', 'e', 'y'};
int i;
if (!aicmac_get_chipid(chipid))
return;
for (i = 0; i < AICMAC_CHIPID_LENGTH; i++) {
out_addr[AICMAC_CHIPID_LENGTH - 1 - i] = chipid[i] ^ key[i];
}
if (port)
out_addr[1] ^= 0x55;
else
out_addr[1] ^= 0xAA;
out_addr[0] &= 0xFE;
out_addr[0] |= 0x02;
}

13
packages/third-party/lwip/contrib/ports/drv/aic/aicmac_macaddr.h vendored Normal file
View File

@@ -0,0 +1,13 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ARTINCHIP_AIC_MACADDR_H_
#define _ARTINCHIP_AIC_MACADDR_H_
void aicmac_get_macaddr_from_chipid(int port, unsigned char out_addr[6]);
#endif

87
packages/third-party/lwip/contrib/ports/drv/aic/sys/ethernetif.c vendored
View File

@@ -11,12 +11,15 @@
#include "lwip/timeouts.h"
#include "netif/etharp.h"
#include "lwip/err.h"
#include "lwip/ethip6.h"
#include <string.h>
#include <aic_core.h>
#include "ethernetif.h"
#include "aic_mac.h"
#include "aic_phy.h"
#include "aicmac_macaddr.h"
#define NETIF_MTU (1500)
#define NETIF_RX_TASK_STACK_SIZE (1024)
#define NETIF_RX_TASK_PRIORITY (TCPIP_THREAD_PRIO-1)
@@ -28,10 +31,6 @@
#define ETH_EVENT_RX_COMPLETE 0x1
#define ETH_EVENT_TX_COMPLETE 0x2
aicos_mutex_t eth_tx_mutex = NULL;
aicos_event_t eth_rx_event = NULL;
extern aicmac_netif_t aic_netif;
extern unsigned long mac_base[MAX_ETH_MAC_PORT];
extern aicmac_dma_desc_ctl_t dctl[MAX_ETH_MAC_PORT];
extern unsigned long mac_irq[MAX_ETH_MAC_PORT];
@@ -39,6 +38,8 @@ extern aicmac_config_t mac_config[MAX_ETH_MAC_PORT];
#if !NO_SYS
static void ethernetif_input_thread(void *pvParameters);
#endif
#if defined(AIC_DEV_GMAC0_MACADDR) | defined(AIC_DEV_GMAC1_MACADDR)
static int hexchar2int(char c)
{
if (c >= '0' && c <= '9') return (c - '0');
@@ -59,40 +60,44 @@ static void hex2bin(unsigned char *bin, char *hex, int binlength)
| hexchar2int(hex[i + 1]));
}
}
#endif
void aicmac_interrupt(void)
//void aicmac_interrupt(void * arg)
irqreturn_t aicmac_interrupt(int irq_num, void *data)
{
aicmac_netif_t *aic_netif = (aicmac_netif_t *)data;
pr_debug("%s\n", __func__);
/* Frame received */
if (aicmac_get_dma_int_status(aic_netif.port, ETH_DMAINTSTS_RI) == SET) {
if (aicmac_get_dma_int_status(aic_netif->port, ETH_DMAINTSTS_RI) == SET) {
/* Clear pending bit */
aicmac_clear_dma_int_pending(aic_netif.port, ETH_DMAINTSTS_RI);
aicmac_clear_dma_int_pending(aic_netif->port, ETH_DMAINTSTS_RI);
#if !NO_SYS
/* Disable interrupt until task complete handle */
aicmac_dis_dma_int(aic_netif.port, ETH_DMAINTEN_RIE);
aicmac_dis_dma_int(aic_netif->port, ETH_DMAINTEN_RIE);
/* Give the semaphore to wakeup LwIP task */
aicos_event_send(eth_rx_event, ETH_EVENT_RX_COMPLETE);
aicos_event_send(aic_netif->eth_rx_event, ETH_EVENT_RX_COMPLETE);
#endif
}
/* Frame transmit complete */
#ifdef CONFIG_MAC_ZERO_COPY_TXBUF
if (aicmac_get_dma_int_status(aic_netif.port, ETH_DMAINTSTS_TI) == SET) {
if (aicmac_get_dma_int_status(aic_netif->port, ETH_DMAINTSTS_TI) == SET) {
/* Disable interrupt until task complete handle */
aicmac_dis_dma_int(aic_netif.port, ETH_DMAINTEN_TIE);
aicmac_dis_dma_int(aic_netif->port, ETH_DMAINTEN_TIE);
/* Clear pending bit */
aicmac_clear_dma_int_pending(aic_netif.port, ETH_DMAINTSTS_TI);
aicmac_clear_dma_int_pending(aic_netif->port, ETH_DMAINTSTS_TI);
/* Give the semaphore to wakeup LwIP task */
aicos_event_send(eth_rx_event, ETH_EVENT_TX_COMPLETE);
aicos_event_send(aic_netif->eth_rx_event, ETH_EVENT_TX_COMPLETE);
}
#endif
/* Clear the interrupt flags. */
/* Clear the Eth DMA Rx IT pending bits */
aicmac_clear_dma_int_pending(aic_netif.port, ETH_DMAINTSTS_NIS);
aicmac_clear_dma_int_pending(aic_netif->port, ETH_DMAINTSTS_NIS);
return IRQ_HANDLED;
}
static void low_level_init(struct netif *netif)
@@ -110,6 +115,8 @@ static void low_level_init(struct netif *netif)
netif->hwaddr[4] = CONFIG_PORT_MAC_ADDR_HIGH & 0xFF;
netif->hwaddr[5] = (CONFIG_PORT_MAC_ADDR_HIGH >> 8) & 0xFF;
aicmac_get_macaddr_from_chipid(aic_netif->port, netif->hwaddr);
#ifdef AIC_DEV_GMAC0_MACADDR
if (aic_netif->port == 0) {
hex2bin(netif->hwaddr, AIC_DEV_GMAC0_MACADDR, 6);
@@ -128,9 +135,13 @@ static void low_level_init(struct netif *netif)
/* Accept broadcast address and ARP traffic */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_IGMP;
#if LWIP_IPV6
netif->flags |= NETIF_FLAG_MLD6;
#endif
/* create binary semaphore used for informing ethernetif of frame reception */
eth_tx_mutex = aicos_mutex_create();
eth_rx_event = aicos_event_create();
aic_netif->eth_tx_mutex = aicos_mutex_create();
aic_netif->eth_rx_event = aicos_event_create();
/* Mac init */
aicmac_init(aic_netif->port);
@@ -152,19 +163,15 @@ static void low_level_init(struct netif *netif)
aicmac_set_dma_rx_desc_int(aic_netif->port, ENABLE);
aicos_request_irq(mac_irq[aic_netif->port],
(irq_handler_t)aicmac_interrupt, 0, NULL, NULL);
(irq_handler_t)aicmac_interrupt, 0, NULL, netif);
/* create the task that handles the ETH_MAC */
aicos_thread_create("eth_rx", NETIF_RX_TASK_STACK_SIZE,
NETIF_RX_TASK_PRIORITY, ethernetif_input_thread, NULL);
NETIF_RX_TASK_PRIORITY, ethernetif_input_thread, netif);
#endif
/* Enable MAC and DMA transmission and reception */
//aicmac_start(aic_netif->port);
/* set phy linkup */
//netif_set_link_up(netif);
/* Phy init */
aicphy_init(aic_netif->port);
aicphy_init(aic_netif);
}
static err_t low_level_output(struct netif *netif, struct pbuf *p)
@@ -195,7 +202,7 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
return ERR_MEM;
}
aicos_mutex_take(eth_tx_mutex, AICOS_WAIT_FOREVER);
aicos_mutex_take(aic_netif->eth_tx_mutex, AICOS_WAIT_FOREVER);
pdesc = dctl[aic_netif->port].tx_desc_p;
/* before read: invalid cache */
@@ -375,7 +382,7 @@ static err_t low_level_output(struct netif *netif, struct pbuf *p)
error:
/* Give semaphore and exit */
aicos_mutex_give(eth_tx_mutex);
aicos_mutex_give(aic_netif->eth_tx_mutex);
return ret;
}
@@ -521,17 +528,18 @@ void ethernetif_input_thread(void *pvParameters)
struct pbuf *p;
uint32_t event = 0;
int ret = 0;
aicmac_netif_t *aic_netif = (aicmac_netif_t *)pvParameters;
for (;;) {
ret = aicos_event_recv(eth_rx_event, ETH_EVENT_RX_COMPLETE|ETH_EVENT_TX_COMPLETE, &event, AICOS_WAIT_FOREVER);
ret = aicos_event_recv(aic_netif->eth_rx_event, ETH_EVENT_RX_COMPLETE|ETH_EVENT_TX_COMPLETE, &event, AICOS_WAIT_FOREVER);
if (ret < 0)
continue;
if (event & ETH_EVENT_RX_COMPLETE) {
TRY_GET_NEXT_FRAME:
p = low_level_input(&aic_netif.netif, false);
p = low_level_input(&aic_netif->netif, false);
if (p != NULL) {
if (ERR_OK != aic_netif.netif.input(p, &aic_netif.netif)) {
if (ERR_OK != aic_netif->netif.input(p, &aic_netif->netif)) {
pbuf_free(p);
} else {
goto TRY_GET_NEXT_FRAME;
@@ -539,22 +547,22 @@ void ethernetif_input_thread(void *pvParameters)
}
#ifdef CONFIG_MAC_ZERO_COPY_TXBUF
while (dctl[aic_netif.port].rx_buf_underrun) {
while (dctl[aic_netif->port].rx_buf_underrun) {
aicos_msleep(100);
pr_info("%s try resume rx underrun!\n", __func__);
aicmac_release_rx_frame(aic_netif.port);
aicmac_release_rx_frame(aic_netif->port);
}
#endif
/* Enable interrupt again */
aicmac_en_dma_int(aic_netif.port, ETH_DMAINTEN_RIE);
aicmac_en_dma_int(aic_netif->port, ETH_DMAINTEN_RIE);
}
if (event & ETH_EVENT_TX_COMPLETE) {
aicmac_confirm_tx_frame(aic_netif.port);
aicmac_confirm_tx_frame(aic_netif->port);
/* Enable interrupt again */
aicmac_en_dma_int(aic_netif.port, ETH_DMAINTEN_TIE);
aicmac_en_dma_int(aic_netif->port, ETH_DMAINTEN_TIE);
}
}
}
@@ -624,15 +632,15 @@ ethernetif_igmp_mac_filter_fun(struct netif *netif,
}
#endif
void ethernetif_input_poll(void)
void ethernetif_input_poll(struct netif *netif)
{
struct pbuf *p;
p = low_level_input(&aic_netif.netif, true);
p = low_level_input(netif, true);
if (p == NULL)
return;
if (ERR_OK != aic_netif.netif.input(p, &aic_netif.netif)) {
if (ERR_OK != netif->input(p, netif)) {
pbuf_free(p);
}
}
@@ -651,6 +659,11 @@ err_t ethernetif_init(struct netif *netif)
netif->output = etharp_output;
netif->linkoutput = low_level_output;
#if LWIP_IPV6
netif->output_ip6 = ethip6_output;
#endif
#if LWIP_IGMP
netif_set_igmp_mac_filter(netif, ethernetif_igmp_mac_filter_fun);
#endif

5
packages/third-party/lwip/contrib/ports/drv/aic/sys/ethernetif.h vendored
View File

@@ -1,4 +1,5 @@
/*
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
@@ -12,6 +13,6 @@
err_t ethernetif_init(struct netif *netif);
err_t ethernetif_input(struct netif *netif);
void ethernetif_input_poll(void);
void ethernetif_input_poll(struct netif *netif);
#endif