diff --git a/bsp/artinchip/sys/d21x/vectors.S b/bsp/artinchip/sys/d21x/vectors.S
index 550fd0d2..4b2defd4 100644
--- a/bsp/artinchip/sys/d21x/vectors.S
+++ b/bsp/artinchip/sys/d21x/vectors.S
@@ -57,7 +57,7 @@ Default_IRQHandler:
     la      sp, g_top_irqstack
 
     /* ipush */
-    addi    sp, sp, -(18 * FREGBYTES)
+    addi    sp, sp, -(18 * REGBYTES)
     STORE   x1, 1 * REGBYTES(sp)    // ra
     csrr    x1, mepc
     STORE   x1, 0 * REGBYTES(sp)    // mepc
@@ -213,7 +213,7 @@ Default_IRQHandler:
     LOAD    x30, 16 * REGBYTES(sp)  // t5
     LOAD    x31, 17 * REGBYTES(sp)  // t6
 
-    addi    sp, sp, (18 * FREGBYTES)
+    addi    sp, sp, (18 * REGBYTES)
 
     /* Restore sp to normal stack */
     csrr    sp, mscratch
diff --git a/kernel/rt-thread/libcpu/risc-v/artinchip/c906/context_gcc.S b/kernel/rt-thread/libcpu/risc-v/artinchip/c906/context_gcc.S
index 8569b9d5..afd38c54 100644
--- a/kernel/rt-thread/libcpu/risc-v/artinchip/c906/context_gcc.S
+++ b/kernel/rt-thread/libcpu/risc-v/artinchip/c906/context_gcc.S
@@ -63,6 +63,12 @@ rt_hw_context_switch_to:
     li      t1, 1
     sw      t1, (t0)
 
+    /* make sure wite instruction is complete */
+    fence
+    lw      t1, (t0)
+    fence
+    sync.is
+
     /* enable global interrup */
     csrsi   mstatus, 8
 
@@ -83,6 +89,11 @@ rt_hw_context_switch_to:
 rt_hw_context_switch:
     .globl rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
+    addi    sp, sp, -(3 * REGBYTES)
+    STORE   t0, 0 * REGBYTES(sp)
+    STORE   t1, 1 * REGBYTES(sp)
+    STORE   t2, 2 * REGBYTES(sp)
+
     /* check rt_thread_switch_interrupt_flag */
     la      t0, rt_thread_switch_interrupt_flag
     lw      t1, (t0)
@@ -99,11 +110,23 @@ rt_hw_context_switch_interrupt:
     /* update to_thread */
     la      t0, rt_interrupt_to_thread
     STORE   a1, (t0)
+
     /* set software interrupt */
     li      t0, TSPEND_INTIP
     li      t1, 1
     sw      t1, (t0)
 
+    /* make sure wite instruction is complete */
+    fence
+    lw      t1, (t0)
+    fence
+    sync.is
+
+    LOAD    t0, 0 * REGBYTES(sp)
+    LOAD    t1, 1 * REGBYTES(sp)
+    LOAD    t2, 2 * REGBYTES(sp)
+    addi    sp, sp, (3 * REGBYTES)
+
     ret
 
 /*
diff --git a/kernel/rt-thread/libcpu/risc-v/artinchip/e9xx/context_gcc.S b/kernel/rt-thread/libcpu/risc-v/artinchip/e9xx/context_gcc.S
index 60acdc86..5b547d28 100644
--- a/kernel/rt-thread/libcpu/risc-v/artinchip/e9xx/context_gcc.S
+++ b/kernel/rt-thread/libcpu/risc-v/artinchip/e9xx/context_gcc.S
@@ -71,6 +71,12 @@ rt_hw_context_switch_to:
     or      t1, t1, t2
     sb      t1, (t0)
 
+    /* make sure wite instruction is complete */
+    fence
+    lb      t1, (t0)
+    fence
+    sync.i
+
     /* enable global interrup */
     csrsi   mstatus, 8
 
@@ -91,6 +97,11 @@ rt_hw_context_switch_to:
 rt_hw_context_switch:
     .globl rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
+    addi    sp, sp, -(3 * REGBYTES)
+    STORE   t0, 0 * REGBYTES(sp)
+    STORE   t1, 1 * REGBYTES(sp)
+    STORE   t2, 2 * REGBYTES(sp)
+
     /* check rt_thread_switch_interrupt_flag */
     la      t0, rt_thread_switch_interrupt_flag
     lw      t1, (t0)
@@ -107,6 +118,7 @@ rt_hw_context_switch_interrupt:
     /* update to_thread */
     la      t0, rt_interrupt_to_thread
     STORE   a1, (t0)
+
     /* set software interrupt */
     li      t0, TSPEND_INTIP
     lb      t1, (t0)
@@ -114,6 +126,17 @@ rt_hw_context_switch_interrupt:
     or      t1, t1, t2
     sb      t1, (t0)
 
+    /* make sure wite instruction is complete */
+    fence
+    lb      t1, (t0)
+    fence
+    sync.i
+
+    LOAD    t0, 0 * REGBYTES(sp)
+    LOAD    t1, 1 * REGBYTES(sp)
+    LOAD    t2, 2 * REGBYTES(sp)
+    addi    sp, sp, (3 * REGBYTES)
+
     ret
 
 /*