From 3c3d3d953e981b5b7b697df07ce4af3c6844c195 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=88=98=E5=8F=AF=E4=BA=AE?= Date: Mon, 8 Jul 2024 13:50:27 +0800 Subject: [PATCH] V1.0.5 --- .../baremetal/bootloader/lib/aicupg/nor_fwc.c | 22 ----- bsp/Kconfig | 82 +++++++++++++++++-- bsp/artinchip/drv_bare/spinor/inc/sfud_cfg.h | 6 ++ bsp/examples_bare/test-spinor/spinor.c | 2 +- bsp/peripheral/spinor_sfud/inc/sfud_def.h | 9 ++ bsp/peripheral/spinor_sfud/src/sfud.c | 47 +++++++++++ bsp/peripheral/spinor_sfud/src/sfud_qe.c | 6 ++ .../drivers/spi/sfud/inc/sfud_cfg.h | 1 + 8 files changed, 145 insertions(+), 30 deletions(-) diff --git a/application/baremetal/bootloader/lib/aicupg/nor_fwc.c b/application/baremetal/bootloader/lib/aicupg/nor_fwc.c index a251f37e..5adae737 100644 --- a/application/baremetal/bootloader/lib/aicupg/nor_fwc.c +++ b/application/baremetal/bootloader/lib/aicupg/nor_fwc.c @@ -79,28 +79,6 @@ s32 nor_fwc_prepare(struct fwc_info *fwc, u32 id) return -1; } - // reset statuts register0 as 0x0 default - uint8_t result; - uint8_t val = 0x0; - uint8_t reg = 0x5; - result = sfud_read_reg(flash, reg, &val); - if (result == SFUD_SUCCESS) { - printf("Read status register0 1, val: %u.\n", val); - } else { - printf("Read status register0 1 failed.\n"); - } - uint8_t *default_0 = 0x0; - result = sfud_write_reg(flash, 0x1, default_0); - if (result == SFUD_SUCCESS) { - printf("Write status register0 0 success.\n"); - } else { - printf("Write status register0 failed.\n"); - } - result = sfud_read_reg(flash, 0x5, &val); - if (result == SFUD_SUCCESS) { - printf("Read status register0 2, val: %u.\n\n", val); - } - #ifdef AIC_SPIENC_BYPASS_IN_UPGMODE spienc_set_bypass(1); #endif diff --git a/bsp/Kconfig b/bsp/Kconfig index 225a0299..0efe403f 100644 --- a/bsp/Kconfig +++ b/bsp/Kconfig @@ -158,6 +158,11 @@ config AIC_SPINOR_SFUD_DEBUG default n depends on LPKG_USING_SFUD +config AIC_SPINOR_SFUD_WP_DEBUG + bool "Enable SPINOR write protection debug" + default y + depends on LPKG_USING_SFUD + config AIC_FB_DRV_DEBUG bool "Enable Display driver debug" default n @@ -170,6 +175,11 @@ config AIC_DISP_MIPI_DBI_DEBUG default n depends on AIC_DISPLAY_DRV && AIC_DISP_MIPI_DBI +config AIC_MAILBOX_DRV_DEBUG + bool "Enable Mailbox driver debug" + default n + depends on AIC_MAILBOX_DRV + config AIC_CACHE_LINE_DEBUG bool "Enable Cache Line debug" default n @@ -218,6 +228,11 @@ config AIC_HRTIMER_DRV_TEST default n depends on AIC_HRTIMER_DRV +config AIC_GPTIMER_DRV_TEST + bool "Enable GPTimer driver test command" + default n + depends on AIC_GPTIMER_DRV + config AIC_QSPI_DRV_TEST bool "Enable SPI driver test command" default n @@ -315,12 +330,17 @@ config AIC_DVP_TEST default n depends on AIC_DVP_DRV +config AIC_MDI_TEST + bool "Enable MDI driver test command" + default n + depends on AIC_MDI_DRV && AIC_MPP_VIN_DEV + config AIC_TP_DRV_TEST bool "Enable touch panel driver test command" default n depends on AIC_TOUCH_PANEL_GT911 || AIC_TOUCH_PANEL_FT7411 \ || AIC_TOUCH_PANEL_GSL1680 || AIC_TOUCH_PANEL_ST16XX \ - || AIC_TOUCH_PANEL_AXS15260 + || AIC_TOUCH_PANEL_AXS15260 || AIC_TOUCH_PANEL_TW31XX config AIC_WDT_DRV_TEST bool "Enable WDT driver test command" @@ -373,6 +393,11 @@ config AIC_PWM_TEST default n depends on AIC_PWM_DRV +config AIC_INPUTCAP_DRV_TEST + bool "Enable INPUTCAP driver test command" + default n + depends on AIC_INPUTCAP_DRV + config AIC_CAP_DRV_TEST bool "Enable CAP driver test command" default n @@ -383,6 +408,11 @@ config AIC_QEP_DRV_TEST default n depends on AIC_QEP_DRV +config AIC_MAILBOX_DRV_TEST + bool "Enable Mailbox driver test command" + default n + depends on AIC_MAILBOX_DRV + config AIC_ADCIM_DM_TEST bool "Enable ADCIM DM test command" default n @@ -422,11 +452,54 @@ config AIC_SOFT_AES_TEST bool "Enable Soft AES ECB test command" default n +config AIC_OSR_CE_BARE_TEST + bool "Enable OSR CE driver test command" + default n + depends on AIC_OSR_CE_DRV + +if AIC_OSR_CE_BARE_TEST + + config AIC_OSR_CE_SKE_BARE_TEST + bool "Enable OSR CE SKE driver test command" + default n + depends on AIC_SKE_DRV + depends on AIC_OSR_CE_BARE_TEST + + config AIC_OSR_CE_PKE_BARE_TEST + bool "Enable OSR CE PKE driver test command" + default n + depends on AIC_PKE_DRV + depends on AIC_OSR_CE_BARE_TEST + + config AIC_OSR_CE_HASH_BARE_TEST + bool "Enable OSR CE HASH driver test command" + default n + depends on AIC_HASH_DRV + depends on AIC_OSR_CE_BARE_TEST + + config AIC_OSR_CE_TRNG_BARE_TEST + bool "Enable OSR CE TRNG driver test command" + default n + depends on AIC_TRNG_DRV + depends on AIC_OSR_CE_BARE_TEST + +endif + config AIC_SID_BARE_TEST bool "Enable SID driver test command" default n depends on AIC_SID_DRV +config AIC_IOPMP_TEST + bool "Enable iopmp driver test command" + default n + depends on !AIC_IOPMP_DRV + +config AIC_IOPMP_BARE_TEST + bool "Enable iopmp driver test command" + default n + depends on AIC_IOPMP_DRV + config AIC_DM_LIB_TEST bool "Enable DM Lib test command" default n @@ -441,17 +514,12 @@ config AIC_MEM_API_TEST bool "Enable memory API test command" default n -config AIC_SE_PM_DRV_TEST - bool "Enable SE PM driver test command" - default n - depends on AIC_PM_DRV - config AIC_FILE_SYSTEM_TEST bool "Enable filesystem test command" default n config AIC_PM_DRV_TEST - bool "Enable PM stability test command" + bool "Enable PM driver test command" depends on AIC_PM_DRV endmenu diff --git a/bsp/artinchip/drv_bare/spinor/inc/sfud_cfg.h b/bsp/artinchip/drv_bare/spinor/inc/sfud_cfg.h index c4f07225..46b54c10 100644 --- a/bsp/artinchip/drv_bare/spinor/inc/sfud_cfg.h +++ b/bsp/artinchip/drv_bare/spinor/inc/sfud_cfg.h @@ -42,6 +42,12 @@ #define SFUD_USING_QSPI +#ifdef AIC_SPINOR_SFUD_WP_DEBUG +#define SFUD_WP_INFO(fmt, ...) printf(fmt"\n", ##__VA_ARGS__) +#else +#define SFUD_WP_INFO(...) do {} while (0) +#endif + /** * Using probe flash JEDEC ID then query defined supported flash chip information table. @see SFUD_FLASH_CHIP_TABLE */ diff --git a/bsp/examples_bare/test-spinor/spinor.c b/bsp/examples_bare/test-spinor/spinor.c index a9d5e1b7..648738d1 100644 --- a/bsp/examples_bare/test-spinor/spinor.c +++ b/bsp/examples_bare/test-spinor/spinor.c @@ -222,7 +222,7 @@ static int do_spinor_reg_read(int argc, char *argv[]) printf("spinor init first.\n"); return 0; } - err = sfud_write_reg(flash, reg, &val); + err = sfud_read_reg(flash, reg, &val); if (err) printf("Read Register failure.\n"); printf("Reg 0x%x, Value: 0x%x\n", reg, val); diff --git a/bsp/peripheral/spinor_sfud/inc/sfud_def.h b/bsp/peripheral/spinor_sfud/inc/sfud_def.h index 8bff98dc..b776b985 100644 --- a/bsp/peripheral/spinor_sfud/inc/sfud_def.h +++ b/bsp/peripheral/spinor_sfud/inc/sfud_def.h @@ -55,6 +55,10 @@ extern "C" { #define SFUD_INFO(...) sfud_log_info(__VA_ARGS__) #endif +#ifndef SFUD_WP_INFO +#define SFUD_WP_INFO(...) sfud_log_info(__VA_ARGS__) +#endif + /* assert for developer. */ #ifdef SFUD_DEBUG_MODE #define SFUD_ASSERT(EXPR) \ @@ -190,6 +194,11 @@ extern void sfud_log_info(const char *format, ...); /* maximum number of erase type support on JESD216 (V1.0) */ #define SFUD_SFDP_ERASE_TYPE_MAX_NUM 4 +/* write protection state mask */ +#ifndef SFUD_WRITE_PROTECTION_MASK +#define SFUD_WRITE_PROTECTION_MASK 0xFC +#endif + /** * status register bits */ diff --git a/bsp/peripheral/spinor_sfud/src/sfud.c b/bsp/peripheral/spinor_sfud/src/sfud.c index 49398969..89996e3a 100644 --- a/bsp/peripheral/spinor_sfud/src/sfud.c +++ b/bsp/peripheral/spinor_sfud/src/sfud.c @@ -75,6 +75,7 @@ static sfud_err read_jedec_id(sfud_flash *flash); sfud_err set_write_enabled(const sfud_flash *flash, bool enabled); static sfud_err set_4_byte_address_mode(sfud_flash *flash, bool enabled); static void make_adress_byte_array(const sfud_flash *flash, uint32_t addr, uint8_t *array); +static sfud_err check_wp_mode(sfud_flash *flash); /** * SFUD initialize by flash device @@ -401,6 +402,7 @@ static sfud_err hardware_init(sfud_flash *flash) { quad_enable_func qe = flash->quad_enable; qe(flash); #endif /* SFUD_USING_QSPI */ + check_wp_mode(flash); return result; } @@ -1027,6 +1029,8 @@ sfud_err set_write_enabled(const sfud_flash *flash, bool enabled) { if (result == SFUD_SUCCESS) { result = sfud_read_status(flash, ®ister_status); + if (register_status & SFUD_WRITE_PROTECTION_MASK) + SFUD_WP_INFO("Flash is in write protection state: 0x%x.\n", register_status); } if (result == SFUD_SUCCESS) { @@ -1120,6 +1124,8 @@ static sfud_err wait_busy(const sfud_flash *flash) { if (result == SFUD_SUCCESS && ((status & SFUD_STATUS_REGISTER_BUSY)) == 0) { break; } + if (status & SFUD_WRITE_PROTECTION_MASK) + SFUD_WP_INFO("Flash is in write protection state: 0x%x.\n", status); /* retry counts */ SFUD_RETRY_PROCESS(flash->retry.delay, retry_times, result); } @@ -1238,3 +1244,44 @@ sfud_err sfud_read_reg(const sfud_flash *flash, uint8_t reg, uint8_t *status) { return flash->spi.wr(&flash->spi, &cmd, 1, status, 1); } + +/** + * ensure the flash is not in write protect state + * + * @note The value of status regester0 is 0 or the falsh may be in the state of write protection. + * + * @param flash flash device + * + * @return result + */ +static sfud_err check_wp_mode(sfud_flash *flash) { + + sfud_err result = SFUD_SUCCESS; + uint8_t reg = 0x5; + uint8_t val = 0x0; + + SFUD_ASSERT(flash); + + result = sfud_read_reg(flash, reg, &val); + if (result == SFUD_SUCCESS) { + if (val & SFUD_WRITE_PROTECTION_MASK) + SFUD_INFO("Flash is in write protection state: 0x%x.\n", val); + } else { + pr_warn("Read status register0 failed.\n"); + return result; + } + + result = sfud_write_status(flash, true, 0x00); + if (result != SFUD_SUCCESS) { + pr_warn("Write status register0 failed.\n"); + return result; + } + + result = sfud_read_reg(flash, reg, &val); + if (result == SFUD_SUCCESS) { + if (val & SFUD_WRITE_PROTECTION_MASK) + SFUD_WP_INFO("Flash is in write protection state: 0x%x.\n", val); + } + + return result; +} \ No newline at end of file diff --git a/bsp/peripheral/spinor_sfud/src/sfud_qe.c b/bsp/peripheral/spinor_sfud/src/sfud_qe.c index 9b6ef12b..61fd73b9 100644 --- a/bsp/peripheral/spinor_sfud/src/sfud_qe.c +++ b/bsp/peripheral/spinor_sfud/src/sfud_qe.c @@ -30,6 +30,8 @@ static int spi_nor_write_16bit_cr_and_check(sfud_flash *flash, uint8_t cr) ret = sfud_read_status(flash, sr_cr); if (ret) return ret; + if (sr_cr[0] & SFUD_WRITE_PROTECTION_MASK) + SFUD_WP_INFO("Flash is in write protection state: 0x%x.\n", sr_cr[0]); sr_cr[1] = cr; @@ -42,6 +44,8 @@ static int spi_nor_write_16bit_cr_and_check(sfud_flash *flash, uint8_t cr) ret = sfud_read_status(flash, sr_cr); if (ret) return ret; + if (sr_cr[0] & SFUD_WRITE_PROTECTION_MASK) + SFUD_WP_INFO("Flash is in write protection state: 0x%x.\n", sr_cr[0]); /* Only check the writable bits */ if (sr_written != (sr_cr[0] & SR1_RW_MSK)) { @@ -83,6 +87,8 @@ static int spi_nor_write_sr1_and_check(sfud_flash *flash, uint8_t sr1) ret = sfud_read_status(flash, &status); if (ret) return ret; + if (status & SFUD_WRITE_PROTECTION_MASK) + SFUD_WP_INFO("Flash is in write protection state: 0x%x.\n", status); if (status!= sr1) { SFUD_INFO("SR1: read back test failed\n"); diff --git a/kernel/rt-thread/components/drivers/spi/sfud/inc/sfud_cfg.h b/kernel/rt-thread/components/drivers/spi/sfud/inc/sfud_cfg.h index 7841306c..5b0bb3a5 100644 --- a/kernel/rt-thread/components/drivers/spi/sfud/inc/sfud_cfg.h +++ b/kernel/rt-thread/components/drivers/spi/sfud/inc/sfud_cfg.h @@ -52,6 +52,7 @@ #define DBG_TAG "SFUD" #include #define SFUD_INFO(...) LOG_I(__VA_ARGS__) +#define SFUD_WP_INFO(...) LOG_I(__VA_ARGS__) /** * Using probe flash JEDEC SFDP parameter.