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v1.1.1

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刘可亮
2024-10-30 16:50:31 +08:00
parent 0ef85b55da
commit 661e71562d
458 changed files with 46555 additions and 12133 deletions
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25
bsp/artinchip/hal/qspi/qspi_internal.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,12 +13,16 @@
extern "C" {
#endif
#define QSPI_WORK_MODE_SYNC_RX_CPU 0
#define QSPI_WORK_MODE_SYNC_TX_CPU 1
#define QSPI_WORK_MODE_ASYNC_RX_CPU 2
#define QSPI_WORK_MODE_ASYNC_TX_CPU 3
#define QSPI_WORK_MODE_ASYNC_RX_DMA 4
#define QSPI_WORK_MODE_ASYNC_TX_DMA 5
#define QSPI_WORK_MODE_SYNC_RX_CPU 0
#define QSPI_WORK_MODE_SYNC_TX_CPU 1
#define QSPI_WORK_MODE_ASYNC_RX_CPU 2
#define QSPI_WORK_MODE_ASYNC_TX_CPU 3
#define QSPI_WORK_MODE_ASYNC_RX_DMA 4
#define QSPI_WORK_MODE_ASYNC_TX_DMA 5
#define QSPI_WORK_MODE_SYNC_DUPLEX_CPU 6
#define QSPI_WORK_MODE_SYNC_DUPLEX_DMA 7
#define QSPI_WORK_MODE_ASYNC_DUPLEX_CPU 8
#define QSPI_WORK_MODE_ASYNC_DUPLEX_DMA 9
#define HAL_QSPI_STATUS_INTERNAL_MSK (0xFFFFUL << 16)
#define HAL_QSPI_STATUS_ASYNC_TDONE (0x1UL << 16)
@@ -30,13 +34,14 @@ extern "C" {
#define QSPI_TRANSFER_DATA_LEN_1M 0x100000
#define QSPI_CPU_DMA_MIN_SPEED_MS (0x800000 >> 10)
void qspi_reg_dump(u32 base);
void show_freq(char *msg, u32 id, u32 hz);
void hal_qspi_fifo_reset(u32 base, u32 fifo);
void hal_qspi_show_ists(u32 id, u32 sts);
u32 qspi_calc_timeout(u32 bus_hz, u32 len);
u32 qspi_master_get_best_div_param(u32 sclk, u32 bus_hz, u32 *div);
int qspi_fifo_write_data(u32 base, u8 *data, u32 len, u32 tmo);
int qspi_fifo_read_data(u32 base, u8 *data, u32 len, u32 tmo_us);
int qspi_wait_transfer_done(u32 base, u32 tmo);
u32 qspi_calc_timeout(u32 bus_hz, u32 len);
#ifdef __cplusplus
}