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v1.1.1

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刘可亮
2024-10-30 16:50:31 +08:00
parent 0ef85b55da
commit 661e71562d
458 changed files with 46555 additions and 12133 deletions
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2
bsp/artinchip/include/hal/hal_audio.h
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@@ -24,7 +24,7 @@
#define AUDIO_TRANSFER_TYPE_AMIC 6
#define MAX_VOLUME_0DB 160
#define AIC_AMIC_DEF_VAL 220
#define AIC_AMIC_DEF_VAL 200
struct aic_audio_config
{

2
bsp/artinchip/include/hal/hal_audio_reg.h
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@@ -190,7 +190,7 @@
#define ADC_CTL2_REG (0xA4)
#define ADC_CTL2_MBIAS_CTL (8)
#define ADC_CTL2_PGA_GAIN_SEL (0xA)
#define ADC_CTL2_PGA_GAIN_SEL (0xF)
#define ADC_CTL2_PGA_GAIN_MASK GENMASK(3, 0)
#define DEFAULT_AUDIO_FREQ (24576000)

58
bsp/artinchip/include/hal/hal_dce.h Normal file
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@@ -0,0 +1,58 @@
/*
* Copyright (c) 2024, ArtInChip Technology CO.,LTD. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Chen JunLong <junlong.chen@artinchip.com>
*/
#ifndef _AIC_HAL_DCE_H_
#define _AIC_HAL_DCE_H_
#include <aic_common.h>
#include <aic_soc.h>
#define DCE_CTL_REG (DCE_BASE + 0x000)
#define DCE_CFG_REG (DCE_BASE + 0x004)
#define DCE_IRQ_REG (DCE_BASE + 0x008)
#define DCE_ISR_REG (DCE_BASE + 0x00C)
#define DCE_ADDR_REG (DCE_BASE + 0x010)
#define DCE_LEN_REG (DCE_BASE + 0x014)
#define DCE_RST_REG (DCE_BASE + 0x040)
#define DCE_CRC_CFG_REG (DCE_BASE + 0x080)
#define DCE_CRC_INIT_REG (DCE_BASE + 0x084)
#define DCE_CRC_XOROUT_REG (DCE_BASE + 0x088)
#define DCE_CRC_RST_REG (DCE_BASE + 0x0C0)
#define DCE_SUM_RST_REG (DCE_BASE + 0x140)
#define DCE_GET_VERSION_REG (DCE_BASE + 0xFFC)
#define DCE_WAIT_CNT 10000
#define DCE_CALC_OK 0
#define DCE_CALC_ERR -1
#define DCE_CALC_TMO -2
#define DCE_ALG_CRC 0x1
#define DCE_ALG_SUM 0x2
#define DCE_ERR_ALL_MSK 0x07000000
#define DCE_CRC_FINISH_MSK 0x01
#define DCE_SUM_FINISH_MSK 0x02
#define OUTPUT_BIT_IN_WORD_REV (0x1 << 0)
#define INPUT_BIT_IN_BYTE_REV (0x1 << 1)
#define INPUT_BIT_IN_WORD_REV (0x1 << 2)
#define INPUT_BYTE_IN_WORD_REV (0x1 << 3)
int hal_dce_init(void);
void hal_dce_deinit(void);
void hal_dce_checksum_start(u8 *data, u32 len);
u32 hal_dce_checksum_wait(void);
u32 hal_dce_checksum_result(void);
void hal_dce_crc32_cfg(u32 out_bit_in_word, u32 input_bit_in_byte,
u32 input_bit_in_word, u32 input_byte_in_word);
void hal_dce_crc32_xor_val(u32 val);
void hal_dce_crc32_start(u32 crc, u8 *data, u32 len);
int hal_dce_crc32_wait(void);
u32 hal_dce_crc32_result(void);
u32 hal_get_version(void);
#endif

10
bsp/artinchip/include/hal/hal_dma.h
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@@ -93,9 +93,7 @@ struct aic_dma_task {
*/
struct aic_dma_task *v_next;
};
#endif
#ifdef AIC_DMA_DRV_V20
#else
struct aic_dma_task {
u32 link_id;
u32 cfg1; /* dma transfer configuration */
@@ -168,12 +166,6 @@ int hal_dma_chan_start(struct aic_dma_chan *chan);
int hal_dma_chan_stop(struct aic_dma_chan *chan);
int hal_dma_chan_pause(struct aic_dma_chan *chan);
int hal_dma_chan_resume(struct aic_dma_chan *chan);
#if defined(AIC_DMA_DRV_V20)
int hal_dma_chan_link_pause(struct aic_dma_chan *chan);
int hal_dma_chan_abandon(struct aic_dma_chan *chan);
int hal_dma_chan_wb_enable(struct aic_dma_chan *chan,
u32 src_addr, u32 dst_addr);
#endif
int hal_dma_chan_terminate_all(struct aic_dma_chan *chan);
int hal_dma_chan_register_cb(struct aic_dma_chan *chan,
dma_async_callback callback,

6
bsp/artinchip/include/hal/hal_i2c.h
View File

@@ -207,6 +207,8 @@ enum i2c_slave_event {
#define I2C_7BIT_ADDR 0
#define I2C_10BIT_ADDR 1
#define I2C_MAX_CHAN 8
#define I2C_INTR_MASTER_MASK (I2C_INTR_RX_UNDER |\
I2C_INTR_RX_FULL |\
I2C_INTR_TX_EMPTY |\
@@ -224,6 +226,10 @@ static inline void hal_i2c_module_enable(aic_i2c_ctrl *i2c_dev)
{
uint32_t reg_val;
reg_val = readl(i2c_dev->reg_base + I2C_CTL);
reg_val |= I2C_CTL_RESTART_ENABLE;
writel(reg_val, i2c_dev->reg_base + I2C_CTL);
reg_val = readl(i2c_dev->reg_base + I2C_ENABLE);
reg_val |= I2C_ENABLE_BIT | I2C_SDA_STUCK_RECOVERY_ENABLE;
writel(reg_val, i2c_dev->reg_base + I2C_ENABLE);

8
bsp/artinchip/include/hal/hal_qspi.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Artinchip Technology Co., Ltd
* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -249,6 +249,8 @@ int hal_qspi_slave_transfer_abort(qspi_slave_handle *h);
int hal_qspi_slave_transfer_count(qspi_slave_handle *h);
void hal_qspi_slave_fifo_reset(qspi_slave_handle *h, u32 fifo);
void hal_qspi_show_ists(u32 id, u32 sts);
#endif //AIC_QSPI_DRV_V11
int hal_qspi_master_init(qspi_master_handle *h, struct qspi_master_config *cfg);
@@ -263,6 +265,10 @@ int hal_qspi_master_transfer_async(qspi_master_handle *h, struct qspi_transfer *
int hal_qspi_master_get_status(qspi_master_handle *h);
void hal_qspi_master_irq_handler(qspi_master_handle *h);
void hal_qspi_master_fifo_reset(qspi_master_handle *h, u32 fifo);
void hal_qspi_fifo_reset(u32 base, u32 fifo);
int hal_spi_master_transfer_sync(qspi_master_handle *h, struct qspi_transfer *t);
int hal_spi_master_transfer_async(qspi_master_handle *h, struct qspi_transfer *t);
int hal_qspi_master_transfer_bit_mode(qspi_master_handle *h, struct qspi_bm_transfer *t);