v1.1.1

bsp/artinchip/sys/d21x/Kconfig.chip

@@ -32,6 +32,16 @@ config CPU_BASE
     default 0x4000000000 if QEMU_RUN
     depends on AIC_CHIP_D21X
 
+config CPU_DRAM_BASE
+    hex
+    default 0x40000000
+    depends on AIC_CHIP_D21X
+
+config CPU_SRAM_BASE
+    hex
+    default 0x00100000
+    depends on AIC_CHIP_D21X
+
 #--------------------------------------------
 # cmu driver global option
 #--------------------------------------------

bsp/artinchip/sys/d21x/aic_gpio_id.c

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <aic_gpio_id.h>
+
+const int aic_gpio_groups_list[] = {
+    PA_GROUP,
+    PB_GROUP,
+    PC_GROUP,
+    PD_GROUP,
+    PE_GROUP,
+    PF_GROUP,
+    PG_GROUP,
+    PU_GROUP,
+};
+
+const int aic_gpio_group_size = sizeof(aic_gpio_groups_list) / sizeof(aic_gpio_groups_list[0]);

bsp/artinchip/sys/d21x/boot_param.c

@@ -67,6 +67,11 @@ void *aic_get_boot_resource(void)
     return (void *)(boot_params_stash.r.a[1]);
 }
 
+void aic_set_boot_resource(void *res_addr)
+{
+    boot_params_stash.r.a[1] = (u32)(uintptr_t)res_addr;
+}
+
 int aic_get_boot_image_id(void)
 {
     return get_boot_image_id(boot_params_stash.r.a[0]);

bsp/artinchip/sys/d21x/include/aic_gpio_id.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Artinchip Technology Co., Ltd
+ * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,10 +19,13 @@ enum {
     PE_GROUP,
     PF_GROUP,
     PG_GROUP,
-    PO_GROUP = 14,
+    PU_GROUP = 14,
     GPIO_GROUP_MAX,
 };
 
+extern const int aic_gpio_groups_list[];
+extern const int aic_gpio_group_size;
+
 #define PA_BASE  0
 #define PB_BASE  32
 #define PC_BASE  64
@@ -37,7 +40,7 @@ enum {
 #define PL_BASE  352
 #define PM_BASE  384
 #define PN_BASE  416
-#define PO_BASE  448
+#define PU_BASE  448
 #define GPIOA(n) (PA_BASE + (n))
 #define GPIOB(n) (PB_BASE + (n))
 #define GPIOC(n) (PC_BASE + (n))
@@ -52,7 +55,7 @@ enum {
 #define GPIOL(n) (PL_BASE + (n))
 #define GPIOM(n) (PM_BASE + (n))
 #define GPION(n) (PN_BASE + (n))
-#define GPIOO(n) (PO_BASE + (n))
+#define GPIOU(n) (PU_BASE + (n))
 
 typedef enum {
     PA0  = GPIOA(0),

bsp/artinchip/sys/d21x/include/boot_param.h

@@ -85,6 +85,7 @@ enum boot_controller aic_get_boot_controller(void);
 int aic_get_boot_image_id(void);
 unsigned long aic_timer_get_us(void);
 void *aic_get_boot_resource(void);
+void aic_set_boot_resource(void *res_addr);
 void *aic_get_boot_resource_from_nand(void *dev, unsigned long pagesize,
                                       nand_read fn);
 void *aic_get_boot_args(void);

bsp/artinchip/sys/d21x/startup_gcc.S

@@ -95,6 +95,10 @@ save_boot_params_ret:
     bltu    a0, a1, 1b
 2:
 
+    /* Reloc private params */
+    la      a5, reloc_private_params
+    jalr    a5
+
 #ifndef __NO_SYSTEM_INIT
     la      a5, SystemInit
     jalr    a5