v1.1.1

bsp/artinchip/sys/g73x/Kconfig.chip

@@ -36,6 +36,16 @@ config CPU_BASE
     default 0xE0000000 if QEMU_RUN
     depends on AIC_CHIP_G73X
 
+config CPU_PSRAM_BASE
+    hex
+    default 0x40000000
+    depends on AIC_CHIP_G73X
+
+config CPU_SRAM_BASE
+    hex
+    default 0x30040000
+    depends on AIC_CHIP_G73X
+
 #--------------------------------------------
 # interrupt global option
 #--------------------------------------------

bsp/artinchip/sys/g73x/aic_gpio_id.c

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <aic_gpio_id.h>
+
+const int aic_gpio_groups_list[] = {
+    PA_GROUP,
+    PB_GROUP,
+    PC_GROUP,
+    PD_GROUP,
+    PE_GROUP,
+    PF_GROUP,
+    PG_GROUP,
+    PU_GROUP,
+};
+
+const int aic_gpio_group_size = sizeof(aic_gpio_groups_list) / sizeof(aic_gpio_groups_list[0]);

bsp/artinchip/sys/g73x/boot_param.c

@@ -67,6 +67,11 @@ void *aic_get_boot_resource(void)
     return (void *)(boot_params_stash.r.a[1]);
 }
 
+void aic_set_boot_resource(void *res_addr)
+{
+    boot_params_stash.r.a[1] = (u32)(uintptr_t)res_addr;
+}
+
 int aic_get_boot_image_id(void)
 {
     return get_boot_image_id(boot_params_stash.r.a[0]);

bsp/artinchip/sys/g73x/include/aic_gpio_id.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, Artinchip Technology Co., Ltd
+ * Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,10 +19,13 @@ enum {
     PE_GROUP,
     PF_GROUP,
     PG_GROUP,
-    PO_GROUP = 14,
+    PU_GROUP = 14,
     GPIO_GROUP_MAX,
 };
 
+extern const int aic_gpio_groups_list[];
+extern const int aic_gpio_group_size;
+
 #define PA_BASE  0
 #define PB_BASE  32
 #define PC_BASE  64
@@ -37,7 +40,7 @@ enum {
 #define PL_BASE  352
 #define PM_BASE  384
 #define PN_BASE  416
-#define PO_BASE  448
+#define PU_BASE  448
 #define GPIOA(n) (PA_BASE + (n))
 #define GPIOB(n) (PB_BASE + (n))
 #define GPIOC(n) (PC_BASE + (n))
@@ -52,7 +55,7 @@ enum {
 #define GPIOL(n) (PL_BASE + (n))
 #define GPIOM(n) (PM_BASE + (n))
 #define GPION(n) (PN_BASE + (n))
-#define GPIOO(n) (PO_BASE + (n))
+#define GPIOU(n) (PU_BASE + (n))
 
 typedef enum {
     PA0  = GPIOA(0),

bsp/artinchip/sys/g73x/include/boot_param.h

@@ -85,6 +85,7 @@ enum boot_controller aic_get_boot_controller(void);
 int aic_get_boot_image_id(void);
 unsigned long aic_timer_get_us(void);
 void *aic_get_boot_resource(void);
+void aic_set_boot_resource(void *res_addr);
 void *aic_get_boot_resource_from_nand(void *dev, unsigned long pagesize,
                                       nand_read fn);
 void *aic_get_boot_args(void);

bsp/artinchip/sys/g73x/rtconfig.py

@@ -1,3 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (C) 2022-2024, ArtInChip Technology Co., Ltd
+
 import os
 import platform
 
@@ -31,11 +35,25 @@ if os.getenv('RTT_EXEC_PATH'):
 # BUILD = 'debug'
 BUILD = 'release'
 if BUILD == 'debug':
-    CFLAGS_DBG = ' -O0 -gdwarf-2'
-    AFLAGS_DBG = ' -gdwarf-2'
+    CFLAGS_DBG = ' -O0 -gdwarf-2 '
+    AFLAGS_DBG = ' -gdwarf-2 '
+    B_AFLAGS = ''
+    B_CFLAGS = ''
+    LFLAGS = ''
+    B_AFLAGS += ' -D_ENABLE_BACK_TRACE_STACK_ '
+    CFLAGS_DBG += ' -fno-omit-frame-pointer '
+    B_AFLAGS +=  ' -D_NO_OMIT_FRAME_POINT_ '
+    #B_CFLAGS += ' -fstack-protector-all '
+    #LFLAGS += ' -Wl,--wrap=__stack_chk_fail '
 else:
     CFLAGS_DBG = ' -O2 -g2'
     AFLAGS_DBG = ''
+    B_AFLAGS = ''
+    B_CFLAGS = ''
+    LFLAGS = ''
+    B_AFLAGS += ' -D_ENABLE_BACK_TRACE_STACK_ '
+    #CFLAGS_DBG += ' -fno-omit-frame-pointer '
+    #B_AFLAGS +=  ' -D_NO_OMIT_FRAME_POINT_ '
 
 prj_out_dir = ''
 if os.environ.get('PRJ_OUT_DIR'):
@@ -73,8 +91,8 @@ if PLATFORM == 'gcc':
     if CPUNAME == 'e906' or CPUNAME == 'e907':
         DEVICE = ' -march=rv32imac_xtheade -mabi=ilp32'
 
-    B_CFLAGS  = ' -c -g -ffunction-sections -fdata-sections -Wall -mcmodel=medlow'
-    B_AFLAGS  = ' -c' + ' -x assembler-with-cpp' + ' -D__ASSEMBLY__'
+    B_CFLAGS  += ' -c -g -ffunction-sections -fdata-sections -Wall -mcmodel=medany '
+    B_AFLAGS  += ' -c' + ' -x assembler-with-cpp' + ' -D__ASSEMBLY__'
     CFLAGS  = DEVICE + B_CFLAGS + CFLAGS_DBG
     AFLAGS  = DEVICE + B_AFLAGS + AFLAGS_DBG
     CXXFLAGS = CFLAGS

bsp/artinchip/sys/g73x/startup_gcc.S

@@ -223,6 +223,10 @@ e907_tcm_init:
     bltu    a0, a1, 1b
 2:
 
+    /* Reloc private params */
+    la      a5, reloc_private_params
+    jalr    a5
+
 #ifndef __NO_SYSTEM_INIT
     la      a5, SystemInit
     jalr    a5

bsp/artinchip/sys/g73x/trap_c.c

@@ -8,6 +8,11 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <rtconfig.h>
+
+#ifdef KERNEL_RTTHREAD
+#include <rtthread.h>
+#endif
+
 #include <csi_core.h>
 
 void (*trap_c_callback)(void);
@@ -37,12 +42,106 @@ void trap_c(uint32_t *regs)
     printf("mtval  : %08lx\n", __get_MTVAL());
     printf("mepc   : %08lx\n", regs[31]);
     printf("mstatus: %08lx\n", regs[32]);
+    printf("\n");
 
-    if (trap_c_callback)
-    {
+    if (trap_c_callback) {
         trap_c_callback();
     }
 
-    while (1);
+    //while (1);
 }
 
+
+#ifdef KERNEL_RTTHREAD
+
+#define CMB_CALL_STACK_MAX_DEPTH 32
+extern size_t __stext;
+extern size_t __etext;
+extern rt_ubase_t g_base_irqstack;
+extern rt_ubase_t g_top_irqstack;
+
+void print_stack(uint32_t *stack_point,uint32_t*stack_point1,uint32_t epc)
+{
+    int i = 0;
+    uint32_t sp = (uint32_t)stack_point;
+    uint32_t pc;
+    uint32_t base_irqstack = (uint32_t)&g_base_irqstack;
+    uint32_t top_irqstack = (uint32_t)&g_top_irqstack;
+    uint32_t stack_addr = (uint32_t) rt_thread_self()->stack_addr;
+    uint32_t stack_size =  rt_thread_self()->stack_size;
+
+    printf("__stext:%p __etext:%p,stack:\n", &__stext, &__etext);
+    if (sp >= base_irqstack && sp <= top_irqstack) {
+        //printf("[%s:%d]base_irqstack::0x%08lx top_irqstack::0x%08lx\n",__FUNCTION__,__LINE__, base_irqstack, top_irqstack);
+        printf("base_irqstack::0x%08lx top_irqstack::0x%08lx\n", base_irqstack, top_irqstack);
+        for (; sp < top_irqstack; sp += sizeof(uint32_t)) {
+            pc  = *((uint32_t *)sp);
+            printf("0x%08lx ", pc);
+            if ((i % 4) == 3) {
+                printf("\n");
+            }
+            i++;
+        }
+        sp = (uint32_t)stack_point1;
+        printf("\n");
+    }
+
+    //printf("[%s:%d]stack_addr:0x%08lx stack_addr_end:0x%08lx\n",__FUNCTION__,__LINE__, stack_addr, stack_addr + stack_size);
+    printf("stack_addr:0x%08lx stack_addr_end:0x%08lx\n",stack_addr, stack_addr + stack_size);
+    for (i = 0; sp < stack_addr + stack_size; sp += sizeof(uint32_t)) {
+        pc  = *((uint32_t *)sp);
+        printf("0x%08lx ", pc);
+        if ((i % 4) == 3) {
+            printf("\n");
+        }
+        i++;
+    }
+    printf("\n\n");
+}
+
+void print_back_trace(int32_t n,rt_ubase_t *regs)
+{
+    int i = 0;
+    printf("back_trace:\n");
+    for(i = 0; i < n; i++) {
+        printf("0x%08lx\n", regs[i]);
+    }
+}
+
+void backtrace_call_stack(rt_ubase_t *stack_point,rt_ubase_t*stack_point1,rt_ubase_t epc)
+{
+    int depth = 0;
+    rt_ubase_t sp = (rt_ubase_t)stack_point;
+    rt_ubase_t pc;
+    size_t code_start_addr = (size_t)&__stext;
+    size_t code_end_addr = (size_t)&__etext;
+    rt_ubase_t base_irqstack = (rt_ubase_t)&g_base_irqstack;
+    rt_ubase_t top_irqstack = (rt_ubase_t)&g_top_irqstack;
+    rt_ubase_t stack_addr = (rt_ubase_t) rt_thread_self()->stack_addr;
+    rt_ubase_t stack_size =  rt_thread_self()->stack_size;
+
+    printf("[%s:%d]__stext:%p __etext:%p\r\n",__FUNCTION__,__LINE__, &__stext, &__etext);
+
+    printf("%08lx\n", epc);
+
+    if (sp >= base_irqstack && sp <= top_irqstack) {
+        for (; sp < top_irqstack; sp += sizeof(rt_ubase_t)) {
+            pc  = *((rt_ubase_t *)sp);
+            if((pc >= code_start_addr) && (pc <= code_end_addr) && (depth < CMB_CALL_STACK_MAX_DEPTH)) {
+                printf("%08lx\n", pc);
+                depth++;
+            }
+        }
+        sp = (rt_ubase_t)stack_point1;
+    }
+
+    depth = 0;
+    for (; sp < stack_addr + stack_size; sp += sizeof(rt_ubase_t)) {
+        pc  = *((rt_ubase_t *)sp);
+        if((pc >= code_start_addr) && (pc <= code_end_addr) && (depth < CMB_CALL_STACK_MAX_DEPTH)) {
+            printf("%08lx\n", pc);
+             depth++;
+        }
+    }
+}
+#endif

bsp/artinchip/sys/g73x/vectors.S

@@ -51,6 +51,14 @@ Default_IRQHandler:
     .long   0x0040000b
 #endif
 
+#if defined(_ENABLE_BACK_TRACE_STACK_) && defined(_NO_OMIT_FRAME_POINT_)
+    addi    sp,sp,-8
+    STORE   s0,(sp)
+    csrr    a0, mepc
+    STORE   a0, 4(sp)
+    addi    s0, sp, 8
+#endif
+
 #ifdef ARCH_RISCV_FPU
     addi    sp, sp, -(20 * FREGBYTES)
 
@@ -138,6 +146,12 @@ Default_IRQHandler:
 
     addi    sp, sp, (20 * FREGBYTES)
 #endif
+
+#if defined(_ENABLE_BACK_TRACE_STACK_) && defined(_NO_OMIT_FRAME_POINT_)
+lw    s0, (sp)
+addi  sp, sp, 8
+#endif
+
 #ifdef __riscv_xthead
     ipop
 #else
@@ -159,8 +173,8 @@ trap:
     csrr    t0, mcause
     blt     t0, x0, .Lirq
     addi    sp, sp, 4
-    la      t0, g_trap_sp
-
+    //la      t0, g_trap_sp
+    mv       t0, sp
     addi    t0, t0, -132
 
     sw      x1,    0(t0)
@@ -207,6 +221,96 @@ trap:
     la      a5, trap_c
     jalr    a5
 
+#ifdef KERNEL_RTTHREAD
+    mv      a0, sp
+    addi    a0, a0, 132
+    csrr    a1, mscratch
+    csrr    a2, mepc
+    la      a5, print_stack
+    jalr    a5
+#endif
+
+
+#if defined(_ENABLE_BACK_TRACE_STACK_) && defined(KERNEL_RTTHREAD)
+#define CALL_STACK_MAX_DEPTH 32
+    la      a0, rt_current_thread
+    beqz    a0, .
+#ifdef _NO_OMIT_FRAME_POINT_
+    mv      t0, sp
+    la      t1, CALL_STACK_MAX_DEPTH
+    slli    t1, t1, 2
+    sub     t0, t0, t1
+    csrr    a1, mepc
+    STORE   a1, (t0)
+    mv      a1, s0
+    li      t1, 1
+1:
+    // check sram addr
+    li      t2, 0x30000000
+    la      t3, AIC_SRAM_TOTAL_SIZE
+    add     t3, t2, t3
+
+    blt     a1, t2, 2f
+    bge     a1, t3, 2f
+
+    addi    a2, a1, -(4)
+    blt     a2, t2, 2f
+    bge     a2, t3, 2f
+
+    addi    a2, a1, -(8)
+    blt     a2, t2, 2f
+    bge     a2, t3, 2f
+
+    j       3f
+2:
+    // check psram addr
+    li      t2, 0x40000000
+    la      t3, AIC_PSRAM_SIZE
+    add     t3, t2, t3
+
+    blt     a1, t2, 4f
+    bge     a1, t3, 4f
+
+    addi    a2, a1, -(4)
+    blt     a2, t2, 4f
+    bge     a2, t3, 4f
+
+    addi    a2, a1, -(8)
+    blt     a2, t2, 4f
+    bge     a2, t3, 4f
+3:
+    // get ra
+    LOAD    a2, -4(a1)
+    slli    t2, t1, 2
+    add     t2, t2, t0
+    STORE   a2, (t2)
+    // get next fp
+    LOAD    a1, -8(a1)
+    //inc call depth
+    addi    t1, t1, 1
+    // check end
+    li  a2, 0xdeadbeef
+    beq a1, a2, 4f
+    la  a2, CALL_STACK_MAX_DEPTH
+    blt t1, a2, 1b
+4:
+    mv      a0, t1
+    mv      a1, t0
+    mv      sp, t0
+    la      a5, print_back_trace
+    jalr    a5
+#else
+    mv      a0, sp
+    addi    a0, a0, 132
+    csrr    a1, mscratch
+    csrr    a2, mepc
+    la      a5, backtrace_call_stack
+    jalr    a5
+#endif
+#endif
+
+
+    j       .
 
 .Lirq:
     lw      t0, 0x0(sp)