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v1.0.3

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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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4
bsp/artinchip/hal/cmu/aic_hal_clk_def_v11.c
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@@ -79,8 +79,8 @@ FPCLK(CLK_PBUS, "pbus", CLK_AHB0, PARENT("ahb0"), CLK_PBUS_REG, 12, -1, 0, 0);
FPCLK(CLK_SYSCFG, "syscfg", CLK_OSC24M, PARENT("osc24m"), CLK_SYSCFG_REG, 12,
-1, 0, 0);
FPCLK(CLK_RTC, "rtc", CLK_OSC32K, PARENT("osc32k"), CLK_RTC_REG, 12, -1, 0, 0);
FPCLK_BASE(CLK_AUDIO_SCLK, "audio_sclk", CLK_PLL_INT1, PARENT("pll_int1"), CLK_AUDIO_REG, 0,
0, 0, 1, 49, 4);
FPCLK_BASE(CLK_AUDIO_SCLK, "audio_sclk", CLK_PLL_INT1, PARENT("pll_int1"), CLK_AUDIO_REG, -1,
-1, 0, 1, 49, 4);
FPCLK(CLK_CODEC, "codec", CLK_AUDIO_SCLK, PARENT("audio_sclk"), CLK_CODEC_REG, 12,
8, 0, 0);
FPCLK(CLK_I2S0, "i2s0", CLK_AUDIO_SCLK, PARENT("audio_sclk"), CLK_I2S0_REG, 12, 8,