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v1.0.3

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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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56
bsp/artinchip/hal/cmu/aic_hal_cpu_clk.c
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@@ -8,8 +8,6 @@
#include <aic_core.h>
#include "aic_hal_clk.h"
#define CPU_CLK_WR_KEY 0x2023
#define to_clk_cpu_mod(_hw) \
container_of(_hw, struct aic_clk_cpu_cfg, comm)
@@ -18,30 +16,55 @@ static u32 clk_cpu_mod_write_enable(struct aic_clk_cpu_cfg *mod, u32 val_tmp)
u32 val = val_tmp;
if (mod->key_bit >= 0) {
val &= ~(mod->key_mask << mod->key_bit);
val |= CPU_CLK_WR_KEY << mod->key_bit;
val |= mod->key_val << mod->key_bit;
}
return val;
}
static int clk_cpu_mod_enable(struct aic_clk_comm_cfg *comm_cfg)
static int
clk_cpu_enable_and_deassert_rst(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 val;
/* enbale clk */
val = readl(cmu_reg(mod->offset_reg));
if (mod->gate_bit >= 0)
val |= (1 << mod->gate_bit);
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
/* deassert rst */
val = readl(cmu_reg(mod->offset_reg));
val |= (1 << MOD_RSTN);
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
return 0;
}
static void clk_cpu_mod_disable(struct aic_clk_comm_cfg *comm_cfg)
static void
clk_cpu_disable_and_assert_rst(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 val;
/* assert rst */
val = readl(cmu_reg(mod->offset_reg));
val &= ~(1 << MOD_RSTN);
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
/* disbale clk */
val = readl(cmu_reg(mod->offset_reg));
if (mod->gate_bit >= 0)
@@ -49,18 +72,23 @@ static void clk_cpu_mod_disable(struct aic_clk_comm_cfg *comm_cfg)
val = clk_cpu_mod_write_enable(mod, val);
writel(val, cmu_reg(mod->offset_reg));
aicos_udelay(30);
}
static int clk_cpu_mod_is_enabled(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 val;
int ret = 0;
val = readl(cmu_reg(mod->offset_reg));
if (mod->gate_bit >= 0)
return val & (1 << mod->gate_bit);
ret = (val & (1 << mod->gate_bit)) ? 1 : 0;
else
ret = 1;
return 1;
return ret;
}
static unsigned long clk_cpu_mod_recalc_rate(struct aic_clk_comm_cfg *comm_cfg,
@@ -74,8 +102,9 @@ static unsigned long clk_cpu_mod_recalc_rate(struct aic_clk_comm_cfg *comm_cfg,
if (parent_index == 1) {
div0 = (readl(cmu_reg(mod->offset_reg)) >> mod->div0_bit) & mod->div0_mask;
rate = parent_rate / (div0 + 1);
} else
} else {
rate = parent_rate;
}
#ifdef CONFIG_DEBUG_ON_FPGA_BOARD_ARTINCHIP
rate = fpga_board_rate[mod->id];
@@ -113,8 +142,13 @@ __out:
static unsigned int clk_cpu_mod_get_parent(struct aic_clk_comm_cfg *comm_cfg)
{
struct aic_clk_cpu_cfg *mod = to_clk_cpu_mod(comm_cfg);
u32 index =
(readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
return (readl(cmu_reg(mod->offset_reg)) >> mod->mux_bit) & mod->mux_mask;
if (index < mod->num_parents)
return mod->parent_ids[index];
else
return 0;
}
static int clk_cpu_mod_set_parent(struct aic_clk_comm_cfg *comm_cfg,
@@ -195,8 +229,8 @@ static long clk_cpu_mod_round_rate(struct aic_clk_comm_cfg *comm_cfg,
const struct aic_clk_ops aic_clk_cpu_ops = {
.enable = clk_cpu_mod_enable,
.disable = clk_cpu_mod_disable,
.enable_clk_deassert_rst = clk_cpu_enable_and_deassert_rst,
.disable_clk_assert_rst = clk_cpu_disable_and_assert_rst,
.is_enabled = clk_cpu_mod_is_enabled,
.recalc_rate = clk_cpu_mod_recalc_rate,
.round_rate = clk_cpu_mod_round_rate,