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v1.0.3

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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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53
bsp/artinchip/include/drv_bare/block_dev.h Normal file
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@@ -0,0 +1,53 @@
/*
* Copyright (c) 2024, Artinchip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Wudehuang <dehuang.wu@artinchip.com>
*/
#ifndef __AIC_BLOCK_DEV_H_
#define __AIC_BLOCK_DEV_H_
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <aic_common.h>
#include <aic_list.h>
#ifdef __cplusplus
extern "C" {
#endif
struct block_dev;
struct block_drv_ops {
u32 (*read)(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
u32 (*write)(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
};
struct block_dev {
struct list_head list;
char *name;
struct block_dev *parent;
/* Partition Offset in parent device, it should be 0 if it is root device */
u32 blk_offset;
u32 blk_size;
u32 blk_cnt;
struct block_drv_ops ops;
void *priv;
};
int block_add_device(struct block_dev *dev);
int block_del_device(struct block_dev *dev);
u32 block_get_device_count(void);
struct block_dev *block_get_device_by_id(u32 id);
struct block_dev *block_get_device(const char *name);
u32 block_read(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
u32 block_write(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
#ifdef __cplusplus
}
#endif
#endif /* __AIC_BLOCK_DEV_H_ */

22
bsp/artinchip/include/drv_bare/mmc.h
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@@ -11,6 +11,7 @@
#include <aic_core.h>
#include <hal_sdmc.h>
#include <aic_partition.h>
struct aic_sdmc_pdata {
ulong base;
@@ -18,7 +19,7 @@ struct aic_sdmc_pdata {
int clk;
u32 is_sdio;
u8 id;
u8 buswidth8;
u8 buswidth;
u8 drv_phase;
u8 smp_phase;
};
@@ -33,7 +34,7 @@ struct aic_sdmc_dev {
u32 bus_width;
u32 clock;
u32 card_caps;
u32 card_capacity;
u32 card_capacity; /* unit: KB*/
u32 host_caps;
u32 valid_ocr;
u32 scr[2];
@@ -42,6 +43,7 @@ struct aic_sdmc_dev {
u32 boot_bus_cond;
u32 part_num;
u32 read_bl_len;
u32 erase_grp_size; /* in 512-byte sectors */
u32 blk_max;
u32 sdmc_id;
u32 max_seg_size;
@@ -69,13 +71,6 @@ struct aic_sdmc_data {
int err;
};
struct aic_partition {
char name[32];
u64 start;
u64 size;
struct aic_partition *next;
};
/**
* struct aic_sdmc - Information about a ArtInChip SDMC host
*
@@ -102,7 +97,6 @@ struct aic_sdmc {
unsigned int clock;
unsigned int sclk_rate;
unsigned int div;
int buswidth;
int ddr_mode;
/* use fifo mode to read and write data */
@@ -199,7 +193,8 @@ struct aic_sdmc {
#define OCR_VOLTAGE_MASK 0x00FFFF80
#define OCR_ACCESS_MODE 0x60000000
#define SECURE_ERASE 0x80000000
#define MMC_ERASE_ARG 0x00000000
#define MMC_SECURE_ERASE 0x80000000
#define MMC_STATUS_MASK (~0x0206BF7F)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
@@ -321,10 +316,15 @@ s32 mmc_init(int id);
s32 mmc_deinit(int id);
u32 mmc_bread(void *priv, u32 start, u32 blkcnt, u8 *dst);
u32 mmc_bwrite(struct aic_sdmc *host, u32 start, u32 blkcnt, const u8 *src);
u32 mmc_berase(struct aic_sdmc *host, u32 start, u32 blkcnt);
struct aic_sdmc *find_mmc_dev_by_index(int id);
struct aic_partition *mmc_new_partition(char *s, u64 start);
void mmc_free_partition(struct aic_partition *part);
struct aic_partition *mmc_create_gpt_part(void);
void sdcard_hotplug_init(void);
int mmc_block_init(struct aic_sdmc *host);
int mmc_block_refresh(struct aic_sdmc *host);
int mmc_block_deinit(struct aic_sdmc *host);
#endif /* _AIC_MMC_H_ */

25
bsp/artinchip/include/drv_bare/mtd.h
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@@ -16,12 +16,32 @@
extern "C" {
#endif
#define MAX_NAND_NAME 32
struct nftl_volume {
char name[MAX_NAND_NAME];
int vol_type;
u32 size;
struct nftl_volume *next;
};
struct nftl_mtd {
char name[MAX_NAND_NAME];
struct nftl_mtd *next;
struct nftl_volume *vols;
};
enum part_attr {
PART_ATTR_MTD = 0,
PART_ATTR_NFTL,
};
#define MAX_MTD_NAME 64
struct mtd_partition {
char name[MAX_MTD_NAME];
u32 start;
u32 size;
struct mtd_partition *next;
enum part_attr attr;
};
struct mtd_dev;
@@ -48,6 +68,7 @@ struct mtd_dev {
unsigned long oobsize;
struct mtd_drv_ops ops;
void *priv;
enum part_attr attr;
};
int mtd_probe(void);
@@ -69,6 +90,10 @@ struct mtd_partition *mtd_parts_parse(char *parts);
void mtd_parts_free(struct mtd_partition *head);
int mtd_contread(struct mtd_dev *mtd, u32 offset, u8 *data, u32 len);
struct nftl_mtd *build_nftl_list(char *nftlvols);
void free_nftl_list(struct nftl_mtd *nftl);
u8 partition_nftl_is_exist(char *mtd_name, struct nftl_mtd *nftl_list);
#ifdef __cplusplus
}
#endif

3
bsp/artinchip/include/drv_bare/xspi_psram.h
View File

@@ -26,6 +26,9 @@ struct aic_xspi
bool inited;
};
#define PSRAM_INIT_OK 0
#define PSRAM_INIT_FAILED 1
u32 aic_xspi_psram_init(void);
#ifdef __cplusplus

2
bsp/artinchip/include/hal/aic_hal_clk.h
View File

@@ -33,6 +33,8 @@ int hal_clk_disable_assertrst(uint32_t clk_id);
int hal_clk_enable_deassertrst_iter(uint32_t clk_id);
void hal_clk_pll_lowpower(void);
const char *hal_clk_get_name(uint32_t clk_id);
#ifdef __cplusplus
}
#endif

25
bsp/artinchip/include/hal/aic_hal_clk_cmu.h
View File

@@ -13,6 +13,8 @@ extern "C" {
struct aic_clk_comm_cfg {
struct aic_clk_ops *ops;
const char *name;
bool enable_count;
};
struct aic_clk_fixed_rate_cfg {
@@ -79,6 +81,7 @@ struct aic_clk_multi_parent_cfg {
struct aic_clk_cpu_cfg {
struct aic_clk_comm_cfg comm;
u32 offset_reg;
u32 key_val;
u8 key_bit;
u8 key_mask;
s32 gate_bit;
@@ -145,12 +148,14 @@ struct aic_clk_ops {
.id = _id, \
.parent_id = 0, \
.rate = _rate, \
.comm.enable_count = 1, \
.comm.ops = &aic_clk_fixed_rate_ops, \
.comm.name = _name, \
}
#define FRCLK(_id, _name, _rate) FRCLK_DEF(_id, _name, _rate)
/* For PLL clock */
#define PLL_DEF(_id, _type, _parent_id, _gen, _fra, _sdm, _flag) \
#define PLL_DEF(_id, _name, _type, _parent_id, _gen, _fra, _sdm, _flag) \
static const struct aic_clk_pll_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_id = _parent_id, \
@@ -160,13 +165,14 @@ struct aic_clk_ops {
.offset_sdm = _sdm, \
.flag = _flag, \
.comm.ops = &aic_clk_pll_ops, \
.comm.name = _name, \
}
#define PLL_INT(_id, _name, _parent_id, _parent_name, _gen, _flag) \
PLL_DEF(_id, AIC_PLL_INT, _parent_id, _gen, 0, 0, _flag)
PLL_DEF(_id, _name, AIC_PLL_INT, _parent_id, _gen, 0, 0, _flag)
#define PLL_FRA(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
PLL_DEF(_id, AIC_PLL_FRA, _parent_id, _gen, _fra, _sdm, _flag)
PLL_DEF(_id, _name, AIC_PLL_FRA, _parent_id, _gen, _fra, _sdm, _flag)
#define PLL_SDM(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
PLL_DEF(_id, AIC_PLL_SDM, _parent_id, _gen, _fra, _sdm, _flag)
PLL_DEF(_id, _name, AIC_PLL_SDM, _parent_id, _gen, _fra, _sdm, _flag)
/* For clocks fixed parent */
#define FPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _bus, _mod, \
@@ -184,6 +190,7 @@ struct aic_clk_ops {
.div_step = _step, \
.flag = _flag, \
.comm.ops = &aic_clk_fixed_parent_ops, \
.comm.name = _name, \
}
#define FPCLK(_id, _name, _parent_id, _parent_name, _reg, _bus, _mod, _div, \
_width) \
@@ -213,19 +220,21 @@ struct aic_clk_ops {
.div0_bit = _div0, \
.div0_mask = ((1 << _div0w) - 1), \
.comm.ops = &aic_clk_multi_parent_ops, \
.comm.name = _name, \
}
#define MPCLK(_id, _name, _parent, _reg, _mod, _mux, _muxw, _div0, _div0w) \
MPCLK_DEF(_id, _name, _parent, _reg, -1, _mod, _mux, _muxw, _div0, _div0w)
#define MPCLK_BUS(_id, _name, _parent, _reg, _bus, _mod, _mux, _muxw, _div0, _div0w) \
MPCLK_DEF(_id, _name, _parent, _reg, _bus, _mod, _mux, _muxw, _div0, _div0w)
#define CPUCLK_DEF(_id, _name, _parent, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, \
#define CPUCLK_DEF(_id, _name, _parent, _reg, _key_val, _key, _keyw, _gate, _mux, _muxw, _div0, \
_div0w) \
static const struct aic_clk_cpu_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_ids = _parent, \
.num_parents = ARRAY_SIZE(_parent), \
.offset_reg = _reg, \
.key_val = _key_val, \
.key_bit = _key, \
.key_mask = _keyw, \
.gate_bit = _gate, \
@@ -234,9 +243,10 @@ struct aic_clk_ops {
.div0_bit = _div0, \
.div0_mask = ((1 << _div0w) - 1), \
.comm.ops = &aic_clk_cpu_ops, \
.comm.name = _name, \
}
#define CPUCLK(_id, _name, _parent, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w) \
CPUCLK_DEF(_id, _name, _parent, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w)
#define CPUCLK(_id, _name, _parent, _key_val, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w) \
CPUCLK_DEF(_id, _name, _parent, _key_val, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w)
/* For display clock */
#define DISPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _divn, \
@@ -255,6 +265,7 @@ struct aic_clk_ops {
.pix_divsel_bit = _pix_divsel, \
.pix_divsel_mask = ((1 << _pix_divsel_width) - 1), \
.comm.ops = &aic_clk_disp_ops, \
.comm.name = _name, \
}
#define DISPCLK(_id, _name, _parent_id, _parent_name, _reg, _divn, _nwidth, \
_divm, _mwidth, _divl, _lwidth, _pix_divsel, \

6
bsp/artinchip/include/hal/aic_hal_dbi.h
View File

@@ -49,6 +49,9 @@
#define DBI_CTL_SPI_FORMAT_MASK GENMASK(27, 24)
#define DBI_CTL_SPI_FORMAT(x) (((x) & 0xF)<<24)
#define DBI_I8080_IDEL BIT(4)
#define DBI_I8080_IDEL_SHIFT 4
#define DBI_I8080_TX_FIFO_EMPTY BIT(1)
#define DBI_I8080_TX_FIFO_EMPTY_SHIFT 1
#define DBI_I8080_RD_FIFO_FLUSH BIT(21)
@@ -58,6 +61,9 @@
#define DBI_I8080_WR_FIFO_DEPTH_MASK GENMASK(6, 0)
#define DBI_I8080_WR_FIFO_DEPTH_SHIFT 0
#define DBI_SPI_IDEL BIT(4)
#define DBI_SPI_IDEL_SHIFT 4
#define DBI_SPI_TX_FIFO_EMPTY BIT(1)
#define DBI_SPI_TX_FIFO_EMPTY_SHIFT 1
#define DBI_SPI_RD_FIFO_FLUSH BIT(21)

35
bsp/artinchip/include/hal/aic_hal_de.h
View File

@@ -22,10 +22,43 @@ enum de_qos_plane {
#if defined(AIC_DE_DRV_V10) || defined(AIC_DE_V10)
#define DE_FREQ (200 * 1000 * 1000)
#define UI_LAYER_NUM 1
#define VI_LAYER_NUM 1
#define UI_LAYER_WIDTH_MAX 4096
#define UI_LAYER_HEIGHT_MAX 4096
#define VI_LAYER_WIDTH_MAX 2048
#define VI_LAYER_HEIGHT_MAX 4096
#define DE_DITHER_WIDTH_MAX 2048
#elif defined(AIC_DE_DRV_V11) || defined(AIC_DE_V11)
#define DE_FREQ (150 * 1000 * 1000)
#define UI_LAYER_NUM 1
#define VI_LAYER_NUM 1
#define UI_LAYER_WIDTH_MAX 4096
#define UI_LAYER_HEIGHT_MAX 4096
#define VI_LAYER_WIDTH_MAX 1280
#define VI_LAYER_HEIGHT_MAX 4096
#define DE_DITHER_WIDTH_MAX 1366
#elif defined(AIC_DE_DRV_V12) || defined(AIC_DE_V12)
#define DE_FREQ (150 * 1000 * 1000)
#define DE_FREQ (100 * 1000 * 1000)
#define UI_LAYER_NUM 1
#define VI_LAYER_NUM 0
#define UI_LAYER_WIDTH_MAX 4096
#define UI_LAYER_HEIGHT_MAX 4096
#define VI_LAYER_WIDTH_MAX 0
#define VI_LAYER_HEIGHT_MAX 0
#define DE_DITHER_WIDTH_MAX 1024
#endif
#define DE_CTRL_DITHER_EN BIT(0)

2
bsp/artinchip/include/hal/aic_hal_dsi.h
View File

@@ -317,7 +317,7 @@ void dsi_set_lane_assign(void *base, u32 ln_assign);
void dsi_set_lane_polrs(void *base, u32 ln_polrs);
void dsi_set_data_clk_polrs(void *base, u32 dc_inv);
void dsi_set_clk_div(void *base, ulong mclk);
void dsi_set_clk_div(void *base, ulong mclk, ulong lp_rate);
void dsi_pkg_init(void *base);
void dsi_phy_init(void *base, ulong mclk, u32 lane);
void dsi_hs_clk(void *base, u32 enable);

64
bsp/artinchip/include/hal/aic_hal_uart.h
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@@ -14,13 +14,71 @@
extern "C" {
#endif
/// definition for usart handle.
typedef void *usart_handle_t;
/* UART register bit definitions */
#define USR_UART_BUSY 0x01
#define USR_UART_TFE 0x04
#define USR_UART_RFNE 0x08
#define LSR_DATA_READY 0x01
#define LSR_THR_EMPTY 0x20
#define IER_RDA_INT_ENABLE 0x01
#define IER_THRE_INT_ENABLE 0x02
#define IIR_RECV_LINE_ENABLE 0x04
#define IIR_NO_ISQ_PEND 0x01
#define FCR_FIFO_EN 0x01
#define FCR_RX_FIFO_RST 0x02
#define FCR_TX_FIFO_RST 0x04
#define FCR_DMA_MODE 0x08
#define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */
#define LCR_PARITY_ENABLE 0x08 /* parity enabled */
#define LCR_PARITY_EVEN 0x10 /* Even parity enabled */
#define LCR_PARITY_ODD 0xef /* Odd parity enabled */
#define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */
#define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */
#define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */
#define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */
#define LCR_STOP_BIT1 0xfb /* 1 stop bit */
#define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */
#define HALT_CHCFG_AT_BUSY 0x02
#define HALT_CHANGE_UPDATE 0x04
#define AIC_LSR_PFE 0x80
#define AIC_LSR_TEMT 0x40
#define AIC_LSR_THRE 0x40
#define AIC_LSR_BI 0x10
#define AIC_LSR_FE 0x08
#define AIC_LSR_PE 0x04
#define AIC_LSR_OE 0x02
#define AIC_LSR_DR 0x01
#define AIC_LSR_TRANS_EMPTY 0x20
#define AIC_IIR_THR_EMPTY 0x02 /* threshold empty */
#define AIC_IIR_RECV_DATA 0x04 /* received data available */
#define AIC_IIR_RECV_LINE 0x06 /* receiver line status */
#define AIC_IIR_CHAR_TIMEOUT 0x0c /* character timeout */
/* ArtInChip specific register fields */
#define AIC_UART_MCR_SIRE 0x40
#define AIC_UART_MCR_RS485 0x80
#define AIC_UART_MCR_RS485S 0xC0
#define AIC_UART_MCR_UART 0x00
#define AIC_UART_MCR_FUNC_MASK 0x3F
#define AIC_UART_EXREG 0xB8 /* RS485 DE Time */
#define AIC_UART_RS485_CTL_MODE 0x80;
#define AIC_UART_RS485_RXBFA 0x08;
#define AIC_UART_RS485_RXAFA 0x04;
#define AIC_USART_SET_RS485_NORMAL 0x20 /**< set rs485 normal enable */
#define AIC_USART_SET_RS485_COMPACT_IO 0x21 /**< set rs485 compact-io enable */
#define AIC_USART_CLR_RS485 0x22 /**< set rs485 disable */
/* definition for usart handle. */
typedef void *usart_handle_t;
/*----- USART Function Codes: -------*/
typedef enum
{
@@ -230,6 +288,8 @@ int32_t hal_usart_uninitialize(usart_handle_t handle);
*/
usart_capabilities_t hal_usart_get_capabilities(int32_t idx);
uint8_t hal_usart_get_irqstatus(int32_t idx);
/**
\brief config usart mode.
\param[in] handle usart handle to operate.

3
bsp/artinchip/include/hal/hal_adcim.h
View File

@@ -13,8 +13,7 @@
int hal_adcim_calibration_set(unsigned int val);
s32 hal_adcim_probe(void);
int hal_adcim_auto_calibration(int adc_val, int st_voltage, int scale,
int adc_max_val);
int hal_adcim_auto_calibration(int adc_val, float def_voltage, int scale);
#ifdef AIC_ADCIM_DM_DRV
void hal_dm_chan_show(void);

2
bsp/artinchip/include/hal/hal_audio.h
View File

@@ -23,6 +23,8 @@
#define AUDIO_TRANSFER_TYPE_DMIC 5
#define AUDIO_TRANSFER_TYPE_AMIC 6
#define MAX_VOLUME_0DB 160
struct aic_audio_config
{
uint32_t samplerate;

23
bsp/artinchip/include/hal/hal_cap.h
View File

@@ -19,14 +19,37 @@
#define CAP_MAX_FREQ 1000000 /* 1MHz */
#ifdef AIC_HRTIMER_DRV
#define AIC_CAP_CH_NUM AIC_HRTIMER_CH_NUM
#endif
#ifdef AIC_CAP_DRV
#define AIC_CAP_CH_NUM AIC_CAPS_CH_NUM
#endif
#define CAP_EVENT3_FLG BIT(4)
struct aic_cap_data {
u8 id;
u32 freq;
float duty;
};
void hal_cap_ch_init(u32 ch);
void hal_cap_ch_deinit(u32 ch);
void hal_cap_int_enable(u32 ch, int enable);
u32 hal_cap_int_sta(void);
u32 hal_cap_is_pending(u32 ch);
int hal_cap_set_freq(u32 ch, u32 freq);
int hal_cap_set_cnt(u32 ch, u32 cnt);
int hal_cap_get(u32 ch);
int hal_cap_in_config(u32 ch);
u32 hal_cap_reg0(u32 ch);
u32 hal_cap_reg1(u32 ch);
u32 hal_cap_reg2(u32 ch);
u32 hal_cap_int_flg(u32 ch);
void hal_cap_clr_flg(u32 ch, u32 stat);
int hal_cap_enable(u32 ch);
int hal_cap_disable(u32 ch);
void hal_cap_cnt_start(u32 ch);

10
bsp/artinchip/include/hal/hal_dma.h
View File

@@ -56,6 +56,14 @@ struct dma_slave_config {
u32 slave_id;
};
struct dma_slave_table {
u32 id;
u32 burst_num;
u32 width_num;
const u32 *burst;
const u32 *width;
};
#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11) \
|| defined(AIC_DMA_DRV_V12)
struct aic_dma_task {
@@ -111,7 +119,7 @@ struct aic_dma_chan {
volatile int lock;
dma_async_callback callback;
void *callback_param;
struct aic_dma_task * desc;
struct aic_dma_task *desc;
};
#define dma_reg(x) (volatile void *)(x + DMA_BASE)

92
bsp/artinchip/include/hal/hal_epwm.h Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: matteo <duanmt@artinchip.com>
*/
#ifndef _ARTINCHIP_HAL_EPWM_H_
#define _ARTINCHIP_HAL_EPWM_H_
#include "aic_common.h"
#define AIC_EPWM_NAME "aic-epwm"
#ifdef CONFIG_FPGA_BOARD_ARTINCHIP
#define EPWM_CLK_RATE 24000000 /* 24 MHz */
#else
#define EPWM_CLK_RATE 200000000 /* 200 MHz */
#endif
#define EPWM_TB_CLK_RATE 25000000 /* 25 MHz */
#define EPWM_INT_FLG BIT(0)
enum aic_epwm_mode {
EPWM_MODE_UP_COUNT = 0,
EPWM_MODE_DOWN_COUNT,
EPWM_MODE_UP_DOWN_COUNT,
EPWM_MODE_STOP_COUNT,
EPWM_MODE_NUM
};
enum aic_epwm_action_type {
EPWM_ACT_NONE = 0,
EPWM_ACT_LOW,
EPWM_ACT_HIGH,
EPWM_ACT_INVERSE,
EPWM_ACT_NUM
};
struct aic_epwm_action {
enum aic_epwm_action_type CBD;
enum aic_epwm_action_type CBU;
enum aic_epwm_action_type CAD;
enum aic_epwm_action_type CAU;
enum aic_epwm_action_type PRD;
enum aic_epwm_action_type ZRO;
};
struct aic_epwm_arg {
u16 available;
u16 id;
enum aic_epwm_mode mode;
u32 tb_clk_rate;
u32 freq;
struct aic_epwm_action action0;
struct aic_epwm_action action1;
u32 period;
u32 duty;
s32 def_level;
};
enum aic_epwm_int_event {
EPWM_CMPA_UP = 0,
EPWM_CMPA_DOWN,
EPWM_CMPB_UP,
EPWM_CMPB_DOWN
};
struct aic_epwm_pulse_para {
u32 prd_ns;
u32 duty_ns;
u32 pulse_cnt;
};
void hal_epwm_ch_init(u32 ch, enum aic_epwm_mode mode, u32 default_level,
struct aic_epwm_action *a0, struct aic_epwm_action *a1);
int hal_epwm_set(u32 ch, u32 duty_ns, u32 period_ns);
int hal_epwm_get(u32 ch, u32 *duty_ns, u32 *period_ns);
int hal_epwm_enable(u32 ch);
int hal_epwm_disable(u32 ch);
u32 hal_epwm_int_sts(u32 ch);
void hal_epwm_clr_int(u32 stat, u32 ch);
void hal_epwm_int_config(u32 ch, u8 irq_mode, u8 enable);
int hal_epwm_init(void);
int hal_epwm_deinit(void);
void hal_epwm_status_show(void);
#endif // end of _ARTINCHIP_HAL_EPWM_H_

8
bsp/artinchip/include/hal/hal_gpai.h
View File

@@ -20,9 +20,9 @@ enum aic_gpai_mode {
};
enum aic_gpai_obtain_data_mode {
AIC_GPAI_OBTAIN_DATA_BY_CPU = 0,
AIC_GPAI_OBTAIN_DATA_BY_DMA = 1,
AIC_GPAI_OBTAIN_DATA_BY_DO = 2
AIC_GPAI_OBTAIN_DATA_BY_CPU = 1,
AIC_GPAI_OBTAIN_DATA_BY_DMA = 2,
AIC_GPAI_OBTAIN_DATA_BY_DO = 3
};
typedef void (*dma_callback)(void *dma_param);
@@ -78,7 +78,7 @@ void hal_gpai_set_ch_num(u32 num);
void aich_gpai_status_show(struct aic_gpai_ch *chan);
s32 hal_gpai_clk_init(void);
void hal_gpai_clk_get(struct aic_gpai_ch *chan);
#if defined(AIC_GPAI_DRV_V11) && defined(AIC_DMA_DRV)
#if defined(AIC_GPAI_DRV_V20) && defined(AIC_DMA_DRV)
void hal_gpai_config_dma(struct aic_gpai_ch *chan);
void hal_gpai_start_dma(struct aic_gpai_ch *chan);
#endif

111
bsp/artinchip/include/hal/hal_hash.h Normal file
View File

@@ -0,0 +1,111 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Xiong Hao <hao.xiong@artinchip.com>
*/
#ifndef _AIC_HAL_HASH_H_
#define _AIC_HAL_HASH_H_
#include <aic_core.h>
#include <aic_common.h>
#define HASH_BASE (CE_BASE + 0x4000)
#define HASH_CTRL (0x000) /* Control register */
#define HASH_CFG (0x004) /* Config register */
#define HASH_SR1 (0x008) /* Status register 1 */
#define HASH_SR2 (0x00C) /* Status register 2 */
#define HASH_PCR_LEN(i) (0x020 + ((i) << 2)) /* message length register */
#define HASH_OUT(i) (0x030 + ((i) << 2)) /* Output register */
#define HASH_IN(i) (0x070 + ((i) << 2)) /* Hash iterator Input register */
#define HASH_VERSION (0x0B0) /* Version register */
#define HASH_M_DIN(i) (0x100 + ((i) << 2)) /* Hash message Input register */
#define HASH_DMA_SA (0x180) /* DMA Source Address register */
#define HASH_DMA_DA (0x184) /* DMA Destination Address register */
#define HASH_DMA_RLEN (0x188) /* DMA Input Length register */
#define HASH_DMA_WLEN (0x18C) /* DMA Output Length register */
#ifdef HMAC_SECURE_PORT_FUNCTION
// If key is from secure port, the max key index(or the number of keys)
#define HMAC_MAX_KEY_IDX (8)
#define HMAC_MAX_SP_KEY_SIZE (64) // For secure port key, max bytes of one key
#endif
// Some register offset
#define HASH_LAST_OFFSET (24)
#define HASH_DMA_OFFSET (17)
#define HASH_INTERRUPTION_OFFSET (16)
// HASH max length
#if (defined(SUPPORT_HASH_SHA384) || defined(SUPPORT_HASH_SHA512) || \
defined(SUPPORT_HASH_SHA512_224) || defined(SUPPORT_HASH_SHA512_256))
#define HASH_DIGEST_MAX_WORD_LEN (16)
#define HASH_BLOCK_MAX_WORD_LEN (32)
#define HASH_TOTAL_LEN_MAX_WORD_LEN (4)
#else
#define HASH_DIGEST_MAX_WORD_LEN (8)
#define HASH_BLOCK_MAX_WORD_LEN (16)
#define HASH_TOTAL_LEN_MAX_WORD_LEN (2)
#endif
#define HASH_ITERATOR_MAX_WORD_LEN HASH_DIGEST_MAX_WORD_LEN
#define HASH_BLOCK_MAX_BYTE_LEN (HASH_BLOCK_MAX_WORD_LEN << 2)
// HASH return code
#define HASH_SUCCESS (0)
#define HASH_BUFFER_NULL (1)
#define HASH_CONFIG_INVALID (2)
#define HASH_INPUT_INVALID (3)
#define HASH_LEN_OVERFLOW (4)
#define HASH_OUTPUT_ZERO_ALL (5)
#define HASH_ERROR (6)
// HASH callback function type
typedef void (*HASH_CALLBACK)(void);
// HASH algorithm definition
typedef enum hash_alg {
HASH_SM3 = 0,
HASH_MD5 = 1,
HASH_SHA256 = 2,
HASH_SHA384 = 3,
HASH_SHA512 = 4,
HASH_SHA1 = 5,
HASH_SHA224 = 6,
HASH_SHA512_224 = 7,
HASH_SHA512_256 = 8,
HASH_SHA3_224 = 9,
HASH_SHA3_256 = 10,
HASH_SHA3_384 = 11,
HASH_SHA3_512 = 12,
} HASH_ALG;
// APIs
u32 hash_get_version(void);
void hash_set_cpu_mode(void);
void hash_set_dma_mode(void);
void hash_set_alg(enum hash_alg alg);
void hash_enable_interruption(void);
void hash_disable_interruption(void);
void hash_set_last_block(u32 tag);
void hash_get_iterator(u8 *iterator, u32 hash_iterator_words);
void hash_set_iterator(u32 *iterator, u32 hash_iterator_words);
void hash_clear_msg_len(void);
void hash_set_msg_total_byte_len(u32 *msg_total_bytes, u32 words);
void hash_set_dma_output_len(u32 bytes);
void hash_start(void);
void hash_wait_till_done(void);
void hash_dma_wait_till_done(HASH_CALLBACK callback);
void hash_input_msg_u8(u8 *msg, u32 msg_bytes);
#ifdef AIC_HASH_DMA
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
void hash_dma_operate(u32 in_h, u32 in_l, u32 out_h, u32 out_l, u32 inByteLen,
HASH_CALLBACK callback);
#else
void hash_dma_operate(u32 *in, u32 *out, u32 inByteLen, HASH_CALLBACK callback);
#endif
#endif
#endif

5
bsp/artinchip/include/hal/hal_i2c.h
View File

@@ -217,6 +217,11 @@ aic_i2c_get_transmit_fifo_num(unsigned long reg_base)
return readl(reg_base + I2C_TXFLR);
}
static inline void aic_i2c_transfer_stop_bit(unsigned long reg_base)
{
writel(I2C_DATA_CMD_STOP, reg_base + I2C_DATA_CMD);
}
static inline void aic_i2c_read_data_cmd(unsigned long reg_base)
{
writel(I2C_DATA_CMD_READ, reg_base + I2C_DATA_CMD);

9
bsp/artinchip/include/hal/hal_i2s.h
View File

@@ -356,6 +356,15 @@ static inline void hal_i2s_rxfifo_output_mode(struct aic_i2s_ctrl *i2s)
writel(reg_val, i2s->reg_base + I2S_FCTL_REG);
}
static inline void hal_i2s_enable_loopback(struct aic_i2s_ctrl *i2s)
{
uint32_t reg_val;
reg_val = readl(i2s->reg_base + I2S_CTL_REG);
reg_val |= I2S_CTL_LOOP;
writel(reg_val, i2s->reg_base + I2S_CTL_REG);
}
int hal_i2s_init(aic_i2s_ctrl *i2s, uint32_t i2s_idx);
int hal_i2s_uninit(aic_i2s_ctrl *i2s);
int hal_i2s_protocol_select(struct aic_i2s_ctrl *i2s, i2s_protocol_t protocol);

220
bsp/artinchip/include/hal/hal_pke.h Normal file
View File

@@ -0,0 +1,220 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Xiong Hao <hao.xiong@artinchip.com>
*/
#ifndef _AIC_HAL_PKE_H_
#define _AIC_HAL_PKE_H_
#include <aic_core.h>
#include <aic_common.h>
#include <hal_pke_eccp_curve.h>
extern const eccp_curve_t sm2_curve[1];
extern const eccp_curve_t sm9_curve[1];
extern const edward_curve_t ed25519[1];
/***************** PKE register *******************/
#define PKE_BASE (CE_BASE + 0x2000)
#define PKE_CTRL (0x000)
#define PKE_CFG (0x004)
#define PKE_MC_PTR (0x008)
#define PKE_RISR (0x00C)
#define PKE_IMCR (0x010)
#define PKE_MISR (0x014)
#define PKE_RT_CODE (0x024)
#define PKE_RAND_SEED (0x040)
#define PKE_EXE_CONF (0x050)
#define PKE_RC_EN (0x060)
#define PKE_RC_KEY (0x064)
#define PKE_RC_D_NONCE (0x068)
#define PKE_RC_A_NONCE (0x06C)
#define PKE_VERSION (0x0FC)
#define PKE_A(a, step) (PKE_BASE + 0x0400 + (a) * (step))
#define PKE_B(a, step) (PKE_BASE + 0x1000 + (a) * (step))
/*********** PKE register action offset ************/
#define PKE_START_CALC (1)
#define PKE_EXE_OUTPUT_AFFINE (0x10)
#define PKE_EXE_R1_MONT_R0_AFFINE (0x09)
#define PKE_EXE_R1_MONT_R0_MONT (0x0A)
#define PKE_EXE_R1_AFFINE_R0_AFFINE (0x05)
#define PKE_EXE_R1_AFFINE_R0_MONT (0x06)
#define PKE_EXE_ECCP_POINT_MUL \
(PKE_EXE_OUTPUT_AFFINE + PKE_EXE_R1_AFFINE_R0_MONT)
#define PKE_EXE_ECCP_POINT_ADD \
(PKE_EXE_OUTPUT_AFFINE + PKE_EXE_R1_AFFINE_R0_AFFINE)
#define PKE_EXE_ECCP_POINT_DBL \
(PKE_EXE_OUTPUT_AFFINE + PKE_EXE_R1_MONT_R0_AFFINE)
#define PKE_EXE_ECCP_POINT_VER \
(PKE_EXE_OUTPUT_AFFINE + PKE_EXE_R1_AFFINE_R0_MONT)
#define PKE_EXE_CFG_ALL_MONT (0x002A)
#define PKE_EXE_CFG_ALL_NON_MONT (0x0000)
#define PKE_EXE_CFG_MODEXP_WITH_PUB (0x0016)
#define PKE_EXE_CFG_MODEXP_WITHOUT_PUB (0x0116)
#define PKE_EXE_CFG_MODEXP_MONT_LADDER (0x0216)
#define PKE_EXE_CFG_MODEXP (0x0316)
/***************** PKE microcode ******************/
#define MICROCODE_PDBL (0x04)
#define MICROCODE_PADD (0x08)
#define MICROCODE_PVER (0x0C)
#define MICROCODE_PMUL (0x10)
#define MICROCODE_MODEXP (0x14)
#define MICROCODE_MODMUL (0x18)
#define MICROCODE_MODINV (0x1C)
#define MICROCODE_MODADD (0x20)
#define MICROCODE_MODSUB (0x24)
#define MICROCODE_MGMR_PRE (0x28)
#define MICROCODE_INTMUL (0x2C)
#define MICROCODE_Ed25519_PMUL (0x30)
#define MICROCODE_Ed25519_PADD (0x34)
#define MICROCODE_C25519_PMUL (0x38)
/*********** some PKE algorithm operand length ************/
#define RSA_MAX_BIT_LEN AIC_PKE_OPERAND_MAX_BIT_LEN
#define DH_MAX_BIT_LEN AIC_PKE_OPERAND_MAX_BIT_LEN
#ifdef AIC_PKE_SEC
#ifdef AIC_PKE_RSA_SUPPORT
#define RSA_SEC
#endif
#ifdef SUPPORT_DH
#define DH_SEC
#endif
#ifdef AIC_PKE_ECDH_SUPPORT
#define ECDH_SEC
#endif
#ifdef AIC_PKE_ECDSA_SUPPORT
#define ECDSA_SEC
#endif
#ifdef AIC_PKE_SM2_SUPPORT
#define SM2_SEC
#endif
#endif
#define OPERAND_MAX_WORD_LEN (GET_WORD_LEN(AIC_PKE_OPERAND_MAX_BIT_LEN))
#define ECCP_MAX_BYTE_LEN (GET_BYTE_LEN(AIC_PKE_ECCP_MAX_BIT_LEN))
#define ECCP_MAX_WORD_LEN (GET_WORD_LEN(AIC_PKE_ECCP_MAX_BIT_LEN))
#define C25519_BYTE_LEN (256 / 8)
#define C25519_WORD_LEN (256 / 32)
#define Ed25519_BYTE_LEN C25519_BYTE_LEN
#define Ed25519_WORD_LEN C25519_WORD_LEN
#define RSA_MAX_WORD_LEN (GET_WORD_LEN(RSA_MAX_BIT_LEN))
#define RSA_MAX_BYTE_LEN (GET_BYTE_LEN(RSA_MAX_BIT_LEN))
#define RSA_MIN_BIT_LEN (512)
#define DH_MAX_WORD_LEN (GET_WORD_LEN(DH_MAX_BIT_LEN))
#define DH_MAX_BYTE_LEN (GET_BYTE_LEN(DH_MAX_BIT_LEN))
#define DH_MIN_BIT_LEN (512)
#define SM2_BIT_LEN (256)
#define SM2_BYTE_LEN (32)
#define SM2_STEPS (SM2_BYTE_LEN + 4)
#define SM2_WORD_LEN (8)
#define SM9_BASE_BIT_LEN (256)
#define SM9_BASE_BYTE_LEN (SM9_BASE_BIT_LEN / 8)
#define SM9_STEPS (SM9_BASE_BYTE_LEN + 4)
#define SM9_BASE_WORD_LEN (SM9_BASE_BIT_LEN / 32)
/******************* PKE return code ********************/
#define PKE_SUCCESS (0)
#define PKE_STOP (1)
#define PKE_NO_MODINV (2)
#define PKE_NOT_ON_CURVE (3)
#define PKE_INVALID_MC (4)
#define PKE_ZERO_ALL (5) //for ECCP input check
#define PKE_INTEGER_TOO_BIG (6) //for ECCP input check
#define PKE_INVALID_INPUT (7)
#define PKE_FINISHED (8)
#define PKE_ERROR (9)
//APIs
s32 pke_init(void);
u32 pke_get_version(void);
u32 pke_set_operand_width(u32 bitLen);
u32 pke_get_operand_bytes(void);
void pke_set_exe_cfg(u32 cfg);
u32 pke_modinv(const u32 *modulus, const u32 *a, u32 *ainv, u32 modWordLen,
u32 aWordLen);
u32 pke_modadd(const u32 *modulus, const u32 *a, const u32 *b, u32 *out,
u32 wordLen);
u32 pke_modsub(const u32 *modulus, const u32 *a, const u32 *b, u32 *out,
u32 wordLen);
u32 pke_add(const u32 *a, const u32 *b, u32 *out, u32 wordLen);
u32 pke_sub(const u32 *a, const u32 *b, u32 *out, u32 wordLen);
u32 pke_mul_internal(const u32 *a, const u32 *b, u32 *out, u32 a_wordLen,
u32 b_wordLen, u32 out_wordLen);
u32 pke_mul(const u32 *a, const u32 *b, u32 *out, u32 ab_wordLen);
u32 pke_pre_calc_mont(const u32 *modulus, u32 bitLen, u32 *H, u32 *n0);
u32 pke_pre_calc_mont_no_output(const u32 *modulus, u32 wordLen);
u32 pke_load_modulus_and_pre_monts(u32 *modulus, u32 *modulus_h,
u32 *modulus_n0, u32 bitLen);
u32 pke_set_modulus_and_pre_monts(u32 *modulus, u32 *modulus_h, u32 *modulus_n0,
u32 bitLen);
u32 pke_modmul_internal(const u32 *a, const u32 *b, u32 *out, u32 wordLen);
u32 pke_modmul(const u32 *modulus, const u32 *a, const u32 *b, u32 *out,
u32 wordLen);
u32 pke_modexp(const u32 *modulus, const u32 *exponent, const u32 *base,
u32 *out, u32 mod_wordLen, u32 exp_wordLen);
u32 pke_modexp_check_input(const u32 *modulus, const u32 *exponent,
const u32 *base, u32 *out, u32 mod_wordLen,
u32 exp_wordLen);
u32 pke_modexp_U8(const u8 *modulus, const u8 *exponent, const u8 *base,
u8 *out, u32 mod_bitLen, u32 exp_bitLen, u32 calc_pre_monts);
u32 pke_mod(u32 *a, u32 aWordLen, u32 *b, u32 *b_h, u32 *b_n0, u32 bWordLen,
u32 *c);
u32 eccp_pointMul(eccp_curve_t *curve, u32 *k, u32 *Px, u32 *Py, u32 *Qx,
u32 *Qy);
u32 eccp_pointAdd(eccp_curve_t *curve, u32 *P1x, u32 *P1y, u32 *P2x, u32 *P2y,
u32 *Qx, u32 *Qy);
//#define ECCP_POINT_DOUBLE //not recommended to define
#ifdef ECCP_POINT_DOUBLE
u32 eccp_pointDouble(eccp_curve_t *curve, u32 *Px, u32 *Py, u32 *Qx, u32 *Qy);
#endif
u32 eccp_pointVerify(eccp_curve_t *curve, u32 *Px, u32 *Py);
u32 eccp_get_pubkey_from_prikey(eccp_curve_t *curve, u8 *priKey, u8 *pubKey);
u32 eccp_getkey(eccp_curve_t *curve, u8 *priKey, u8 *pubKey);
#ifdef SUPPORT_C25519
u32 x25519_pointMul(mont_curve_t *curve, u32 *k, u32 *Pu, u32 *Qu);
u32 ed25519_pointMul(edward_curve_t *curve, u32 *k, u32 *Px, u32 *Py, u32 *Qx,
u32 *Qy);
u32 ed25519_pointAdd(edward_curve_t *curve, u32 *P1x, u32 *P1y, u32 *P2x,
u32 *P2y, u32 *Qx, u32 *Qy);
#endif
#ifdef AIC_PKE_SEC
u32 pke_sec_init(void);
u32 pke_sec_uninit(void);
u32 pke_modexp_ladder(const u32 *modulus, const u32 *exponent, const u32 *base,
u32 *out, u32 mod_wordLen, u32 exp_wordLen);
u32 pke_modexp_with_pub(const u32 *modulus, const u32 *exponent, const u32 *pub,
const u32 *base, u32 *out, u32 mod_wordLen,
u32 exp_wordLen, u32 pub_wordLen);
u32 pke_modexp_without_pub(const u32 *modulus, const u32 *exponent,
const u32 *base, u32 *out, u32 mod_wordLen,
u32 exp_wordLen);
u32 eccp_pointMul_sec(eccp_curve_t *curve, u32 *k, u32 *Px, u32 *Py, u32 *Qx,
u32 *Qy);
#endif
#endif

207
bsp/artinchip/include/hal/hal_pke_eccp_curve.h Normal file
View File

@@ -0,0 +1,207 @@
#ifndef ECCP_CURVE_H
#define ECCP_CURVE_H
#include <aic_common.h>
#include "pke_common.h"
#ifdef __cplusplus
extern "C" {
#endif
//sample ecc GF(p) curve
/*
#define SUPPORT_BRAINPOOLP160R1
#define SUPPORT_BRAINPOOLP192R1
#define SUPPORT_BRAINPOOLP224R1
#define SUPPORT_BRAINPOOLP256R1
#define SUPPORT_BRAINPOOLP320R1
#define SUPPORT_BRAINPOOLP384R1
#define SUPPORT_BRAINPOOLP512R1
#define SUPPORT_SECP160R1
#define SUPPORT_SECP160R2
#define SUPPORT_SECP192R1
#define SUPPORT_SECP224R1
*/
#define SUPPORT_SECP256R1
/*
#define SUPPORT_SECP384R1
#if (AIC_PKE_ECCP_MAX_BIT_LEN >= 521)
#define SUPPORT_SECP521R1
#endif
#define SUPPORT_SECP160K1
#define SUPPORT_SECP192K1
#define SUPPORT_SECP224K1
#define SUPPORT_SECP256K1
#define SUPPORT_BN256
#if (AIC_PKE_ECCP_MAX_BIT_LEN >= 638)
#define SUPPORT_BN638
#endif
*/
// eccp curve struct
#ifdef PKE_HP
typedef struct
{
u32 eccp_p_bitLen; //bit length of prime p
u32 eccp_n_bitLen; //bit length of order n
u32 *eccp_p;
u32 *eccp_p_h;
u32 *eccp_a;
u32 *eccp_b;
u32 *eccp_Gx;
u32 *eccp_Gy;
u32 *eccp_n;
u32 *eccp_n_h;
u32 *eccp_half_Gx;
u32 *eccp_half_Gy;
} eccp_curve_t;
#else
typedef struct
{
u32 eccp_p_bitLen; //bit length of prime p
u32 eccp_n_bitLen; //bit length of order n
u32 *eccp_p; //prime p
u32 *eccp_p_h;
u32 *eccp_p_n0;
u32 *eccp_a;
u32 *eccp_b;
u32 *eccp_Gx;
u32 *eccp_Gy;
u32 *eccp_n; //order of curve or point(Gx,Gy)
u32 *eccp_n_h;
u32 *eccp_n_n0;
} eccp_curve_t;
#endif
#ifdef SUPPORT_BRAINPOOLP160R1
extern const eccp_curve_t brainpoolp160r1[1];
#endif
#ifdef SUPPORT_BRAINPOOLP192R1
extern const eccp_curve_t brainpoolp192r1[1];
#endif
#ifdef SUPPORT_BRAINPOOLP224R1
extern const eccp_curve_t brainpoolp224r1[1];
#endif
#ifdef SUPPORT_BRAINPOOLP256R1
extern const eccp_curve_t brainpoolp256r1[1];
#endif
#ifdef SUPPORT_BRAINPOOLP320R1
extern const eccp_curve_t brainpoolp320r1[1];
#endif
#ifdef SUPPORT_BRAINPOOLP384R1
extern const eccp_curve_t brainpoolp384r1[1];
#endif
#ifdef SUPPORT_BRAINPOOLP512R1
extern const eccp_curve_t brainpoolp512r1[1];
#endif
#ifdef SUPPORT_SECP160R1
extern const eccp_curve_t secp160r1[1];
#endif
#ifdef SUPPORT_SECP160R2
extern const eccp_curve_t secp160r2[1];
#endif
#ifdef SUPPORT_SECP192R1
extern const eccp_curve_t secp192r1[1];
#endif
#ifdef SUPPORT_SECP224R1
extern const eccp_curve_t secp224r1[1];
#endif
#ifdef SUPPORT_SECP256R1
extern const eccp_curve_t secp256r1[1];
#endif
#ifdef SUPPORT_SECP384R1
extern const eccp_curve_t secp384r1[1];
#endif
#ifdef SUPPORT_SECP521R1
extern const eccp_curve_t secp521r1[1];
#endif
#ifdef SUPPORT_SECP160K1
extern const eccp_curve_t secp160k1[1];
#endif
#ifdef SUPPORT_SECP192K1
extern const eccp_curve_t secp192k1[1];
#endif
#ifdef SUPPORT_SECP224K1
extern const eccp_curve_t secp224k1[1];
#endif
#ifdef SUPPORT_SECP256K1
extern const eccp_curve_t secp256k1[1];
#endif
#ifdef SUPPORT_BN256
extern const eccp_curve_t bn256[1];
#endif
#ifdef SUPPORT_BN638
extern const eccp_curve_t bn638[1];
#endif
/********* Curve25519 struct *********/
typedef struct
{
u32 p_bitLen; //bit length of prime p
u32 n_bitLen; //bit length of order n
u32 *p;
u32 *p_h;
#ifndef PKE_HP
u32 *p_n0;
#endif
u32 *a24; //(A-2)/4
u32 *u;
u32 *v;
u32 *n; //order of curve or point(Gx,Gy)
u32 *n_h;
#ifndef PKE_HP
u32 *n_n0;
#endif
u32 *h;
} mont_curve_t;
/********* Edward Curve 25519 struct *********/
typedef struct
{
u32 p_bitLen; //bit length of prime p
u32 n_bitLen; //bit length of order n
u32 *p;
u32 *p_h;
#ifndef PKE_HP
u32 *p_n0;
#endif
u32 *d;
u32 *Gx;
u32 *Gy;
u32 *n; //order of curve or point(Gx,Gy)
u32 *n_h;
#ifndef PKE_HP
u32 *n_n0;
#endif
u32 *h;
} edward_curve_t;
#ifdef __cplusplus
}
#endif
#endif

36
bsp/artinchip/include/hal/hal_pke_ecdh.h Normal file
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@@ -0,0 +1,36 @@
#ifndef ECDH_H
#define ECDH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_pke.h"
//ECDH return code
#define ECDH_SUCCESS PKE_SUCCESS
#define ECDH_POINTOR_NULL (PKE_SUCCESS+0x60U)
#define ECDH_INVALID_INPUT (PKE_SUCCESS+0x61U)
#define ECDH_ZERO_ALL (PKE_SUCCESS+0x62U)
#define ECDH_INTEGER_TOO_BIG (PKE_SUCCESS+0x63U)
//APIs
u32 ecdh_compute_key(eccp_curve_t *curve, u8 *local_prikey, u8 *peer_pubkey, u8 *key,
u32 keyByteLen, KDF_FUNC kdf);
#ifdef ECDH_SEC
//ECDH return code(secure version)
#define ECDH_SUCCESS_S (0x8B9BC1E1U)
#define ECDH_ERROR_S (0xCBC192A3U)
u32 ecdh_compute_key_s(eccp_curve_t *curve, u8 *local_prikey, u8 *peer_pubkey, u8 *key,
u32 keyByteLen, KDF_FUNC kdf);
#endif
#ifdef __cplusplus
}
#endif
#endif

39
bsp/artinchip/include/hal/hal_pke_ecdsa.h Normal file
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@@ -0,0 +1,39 @@
#ifndef ECDSA_H
#define ECDSA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "hal_pke.h"
//ECDSA return code
#define ECDSA_SUCCESS PKE_SUCCESS
#define ECDSA_POINTOR_NULL (PKE_SUCCESS+0x50U)
#define ECDSA_INVALID_INPUT (PKE_SUCCESS+0x51U)
#define ECDSA_ZERO_ALL (PKE_SUCCESS+0x52U)
#define ECDSA_INTEGER_TOO_BIG (PKE_SUCCESS+0x53U)
#define ECDSA_VERIFY_FAILED (PKE_SUCCESS+0x54U)
//APIs
u32 ecdsa_sign(eccp_curve_t *curve, u8 *E, u32 EByteLen, u8 *rand_k, u8 *priKey,
u8 *signature);
u32 ecdsa_verify(eccp_curve_t *curve, u8 *E, u32 EByteLen, u8 *pubKey, u8 *signature);
#ifdef ECDSA_SEC
//ECDSA return code(secure version)
#define ECDSA_SUCCESS_S (0x7D5FEB14U)
#define ECDSA_ERROR_S (0xB4C0BC5AU)
u32 ecdsa_sign_s(eccp_curve_t *curve, u8 *E, u32 EByteLen, u8 *rand_k, u8 *priKey,
u8 *signature);
u32 ecdsa_verify_s(eccp_curve_t *curve, u8 *E, u32 EByteLen, u8 *pubKey, u8 *signature);
#endif
#ifdef __cplusplus
}
#endif
#endif

14
bsp/artinchip/include/hal/hal_psadc.h
View File

@@ -29,14 +29,14 @@ struct aic_psadc_ch {
aicos_sem_t complete;
};
void aich_psadc_enable(int enable);
void aic_psadc_single_queue_mode(int enable);
void aich_psadc_qc_irq_enable(int enable);
int aich_psadc_ch_init(struct aic_psadc_ch *chan, u32 pclk);
irqreturn_t aich_psadc_isr(int irq, void *arg);
int aich_psadc_read(struct aic_psadc_ch *chan, u32 *val, u32 timeout);
void hal_psadc_enable(int enable);
void hal_psadc_single_queue_mode(int enable);
void hal_psadc_qc_irq_enable(int enable);
int hal_psadc_ch_init(struct aic_psadc_ch *chan, u32 pclk);
irqreturn_t hal_psadc_isr(int irq, void *arg);
int hal_psadc_read(struct aic_psadc_ch *chan, u32 *val, u32 timeout);
struct aic_psadc_ch *hal_psadc_ch_is_valid(u32 ch);
void hal_psadc_set_ch_num(u32 num);
void aich_psadc_status_show(struct aic_psadc_ch *chan);
void hal_psadc_status_show(struct aic_psadc_ch *chan);
#endif

16
bsp/artinchip/include/hal/hal_pwm.h
View File

@@ -63,6 +63,19 @@ struct aic_pwm_arg {
enum pwm_polarity polarity;
};
enum aic_pwm_int_event {
PWM_CMPA_UP = 0,
PWM_CMPA_DOWN,
PWM_CMPB_UP,
PWM_CMPB_DOWN
};
struct aic_pwm_pulse_para {
u32 prd_ns;
u32 duty_ns;
u32 pulse_cnt;
};
void hal_pwm_ch_init(u32 ch, enum aic_pwm_mode mode, u32 default_level,
struct aic_pwm_action *a0, struct aic_pwm_action *a1);
int hal_pwm_set(u32 ch, u32 duty_ns, u32 period_ns);
@@ -70,6 +83,9 @@ int hal_pwm_get(u32 ch, u32 *duty_ns, u32 *period_ns);
int hal_pwm_set_polarity(u32 ch, enum pwm_polarity polarity);
int hal_pwm_enable(u32 ch);
int hal_pwm_disable(u32 ch);
u32 hal_pwm_int_sts(void);
void hal_pwm_clr_int(u32 stat);
void hal_pwm_int_config(u32 ch, u8 irq_mode, u8 enable);
int hal_pwm_init(void);
int hal_pwm_deinit(void);

4
bsp/artinchip/include/hal/hal_qspi.h
View File

@@ -139,8 +139,8 @@ struct qspi_slave_state {
struct qspi_bm_transfer {
u8 *tx_data;
u8 *rx_data;
u32 rx_len;
u32 tx_len;
u32 rx_bits_len;
u32 tx_bits_len;
};
#ifdef AIC_QSPI_DRV_V11

1
bsp/artinchip/include/hal/hal_rtp.h
View File

@@ -104,5 +104,6 @@ s32 hal_rtp_ebuf_read(struct aic_rtp_ebuf *ebuf, struct aic_rtp_event *e);
s32 hal_rtp_clk_init(void);
s32 hal_rtp_register_callback(rtp_callback_t callback);
s32 hal_rtp_ebuf_sync(struct aic_rtp_ebuf *ebuf);
u32 hal_rtp_pdeb_valid_check(struct aic_rtp_dev *rtp);
#endif

133
bsp/artinchip/include/hal/hal_ske.h Normal file
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@@ -0,0 +1,133 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Xiong Hao <hao.xiong@artinchip.com>
*/
#ifndef _AIC_HAL_SKE_H_
#define _AIC_HAL_SKE_H_
#include <aic_core.h>
#include <aic_common.h>
#define SKE_BASE (CE_BASE + 0x1000)
#define SKE_CTRL (0x000) /* SKE Control Register */
#define SKE_CFG (0x004) /* SKE Config Register */
#define SKE_SR1 (0x008) /* SKE Status Register 1 */
#define SKE_SR2 (0x00C) /* SKE Status Register 2 */
#define SKE_AES_CFG (0x060) /* SKE AES key length config Register */
#define SKE_IV(i) (0x070 + (i << 2)) /* Initial Vector */
#define SKE_KEY(i) (0x080 + (i << 2)) /* Key*/
#define SKE_RNG_SD(i) (0x100 + (i << 2)) /* pseudo-random seed */
#define SKE_RNG_CTRL (0x130) /* pseudo-random Control Register */
#define SKE_VERSION (0x140) /* SKE version Register */
#define SKE_IN(i) (0x200 + (i << 2)) /* SKE Input Register */
#define SKE_OUT(i) (0x210 + (i << 2)) /* SKE Output Register */
// Some register offset
#define SKE_REVERSE_BYTE_ORDER_IN_WORD_OFFSET (12)
#define SKE_RESET_OFFSET (16)
#define SKE_MODE_OFFSET (9)
#define SKE_CRYPTO_OFFSET (8)
#define SKE_UPDATE_KEY_OFFSET (16)
#define SKE_SECURE_PORT_OFFSET (17)
#define SKE_UPDATE_IV_OFFSET (18)
#define SKE_ERR_CFG_OFFSET (8)
#define SKE_SET_SEED_BYTE_LEN (36)
// SKE return code
#define SKE_SUCCESS (0)
#define SKE_BUFFER_NULL (1)
#define SKE_CONFIG_INVALID (2)
#define SKE_INPUT_INVALID (3)
#define SKE_RUNTIME_ALARM (4)
#define SKE_PADDING_ERROR (5)
#define SKE_ERROR (6)
// SKE Operation Mode
typedef enum ske_mode{
SKE_MODE_ECB = 0, // ECB Mode
SKE_MODE_CBC = 1, // CBC Mode
SKE_MODE_CFB = 2, // CFB Mode
SKE_MODE_OFB = 3, // OFB Mode
SKE_MODE_CTR = 4, // CTR Mode
SKE_MODE_XTS = 5, // XTS Mode
SKE_MODE_CMAC = 6, // CMAC Mode
SKE_MODE_CBC_MAC = 7, // CBC-MAC Mode
SKE_MODE_GCM = 8, // GCM Mode
SKE_MODE_CCM = 9, // CCM Mode
SKE_MODE_GMAC = 10, // GMAC Mode
} SKE_MODE;
// SKE Crypto Action
typedef enum {
SKE_CRYPTO_ENCRYPT = 0, // encrypt
SKE_CRYPTO_DECRYPT, // decrypt
} SKE_CRYPTO;
// SKE MAC Action
typedef enum {
SKE_GENERATE_MAC = SKE_CRYPTO_ENCRYPT,
SKE_VERIFY_MAC = SKE_CRYPTO_DECRYPT,
} SKE_MAC;
// SKE Algorithm
typedef enum ske_alg{
SKE_ALG_DES = 0, // DES
SKE_ALG_TDES_128 = 1, // TDES 128 bits key
SKE_ALG_TDES_192 = 2, // TDES 192 bits key
SKE_ALG_TDES_EEE_128 = 3, // TDES_EEE 128 bits key
SKE_ALG_TDES_EEE_192 = 4, // TDES_EEE 192 bits key
SKE_ALG_AES_128 = 5, // AES 128 bits key
SKE_ALG_AES_192 = 6, // AES 192 bits key
SKE_ALG_AES_256 = 7, // AES 256 bits key
SKE_ALG_SM4 = 8, // SM4
} SKE_ALG;
// SKE padding scheme
typedef enum {
SKE_NO_PADDING = 0,
SKE_ANSI_X923_PADDING,
SKE_PKCS_5_7_PADDING,
SKE_ISO_7816_4_PADDING,
SKE_ZERO_PADDING, //hardware does not support, just for CBC-MAC
} SKE_PADDING;
// SKE block length
typedef struct {
#if (defined(CONFIG_SKE_SUPPORT_MUL_THREAD))
SKE_ALG alg;
u8 *key;
u16 sp_key_idx;
u32 key_buf[32 / 4]; //hw not support xts directly
#endif
u32 iv[4];
SKE_MODE mode;
SKE_CRYPTO crypto;
u8 block_bytes;
u8 block_words;
SKE_PADDING padding;
} SKE_CTX;
//APIs
s32 ske_init(void);
u32 ske_get_version(void);
void ske_reset(void);
void ske_set_endian_uint32(void);
void ske_set_crypto(SKE_CRYPTO crypto);
void ske_set_alg(SKE_ALG ske_alg);
void ske_set_mode(SKE_MODE mode);
u32 ske_set_seed(void);
u32 ske_check_runtime_alarm(void);
u32 ske_check_config(void);
void ske_start(void);
u32 ske_wait_till_done(void);
void ske_set_key_uint32(u32 *key, u32 idx, u32 key_words);
void ske_set_iv_uint32(u32 mode, u32 *iv, u32 block_words);
void ske_simple_set_input_block(u32 *in, u32 block_words);
void ske_simple_get_output_block(u32 *out, u32 block_words);
#endif

1
bsp/artinchip/include/hal/hal_syscfg.h
View File

@@ -56,5 +56,6 @@ s32 syscfg_fpga_de_clk_sel_by_div(u8 sclk, u8 pixclk);
void syscfg_fpga_lcd_io_set(u32 val);
s32 hal_syscfg_probe(void);
u32 syscfg_read_ldo_cfg(void);
#endif

75
bsp/artinchip/include/hal/hal_trng.h Normal file
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@@ -0,0 +1,75 @@
/*
* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* Authors: Xiong Hao <hao.xiong@artinchip.com>
*/
#ifndef _AIC_HAL_TRNG_H_
#define _AIC_HAL_TRNG_H_
#include <aic_common.h>
// TRNG register address
#define TRNG_BASE (CE_BASE + 0x5000)
#define TRNG_CR (0x000)
#define TRNG_MSEL (0x004)
#define TRNG_SR (0x008)
#define TRNG_DR (0x00C)
#define TRNG_RESEED (0x010)
#define RO_CLK_EN (0x014)
#define RO_SRC_EN1 (0x018)
#define RO_SRC_EN2 (0x01C)
#define TRNG_HT_CR (0x020)
#define TRNG_HT_SR (0x024)
#define TRNG_VERSION (0x030)
// TRNG freq config
#define TRNG_RO_FREQ_4 (0)
#define TRNG_RO_FREQ_8 (1)
#define TRNG_RO_FREQ_16 (2)
#define TRNG_RO_FREQ_32 (3) //default
// TRNG action offset
#define TRNG_GLOBAL_INT_OFFSET (24)
#define TRNG_READ_EMPTY_INT_OFFSET (17)
#define TRNG_DATA_INT_OFFSET (16)
#define TRNG_FREQ_OFFSET (16)
// TRNG return code
#define TRNG_SUCCESS (0)
#define TRNG_BUFFER_NULL (1)
#define TRNG_INVALID_INPUT (2)
#define TRNG_INVALID_CONFIG (3)
#define TRNG_HT_ERROR (4)
#define TRNG_TIMEOUT_ERROR (5)
#define TRNG_ERROR (6)
typedef u32 (*GET_RAND_WORDS)(u32 *a, u32 words);
//API
u32 trng_get_version(void);
void trng_global_int_enable(void);
void trng_global_int_disable(void);
void trng_empty_read_int_enable(void);
void trng_empty_read_int_disable(void);
void trng_data_int_enable(void);
void trng_data_int_disable(void);
void trng_enable(void);
void trng_disable(void);
#ifdef AIC_TRNG_RO_ENTROPY
u32 trng_ro_entropy_config(u8 cfg);
u32 trng_ro_sub_entropy_config(u8 sn, u16 cfg);
void trng_set_mode(u8 with_post_processing);
void trng_reseed(void);
u32 trng_set_freq(u8 freq);
u32 get_rand_uint32(u32 *a, u32 words);
u32 get_rand_uint32_without_reseed(u32 *a, u32 words);
u32 get_rand_uint32_with_reseed(u32 *a, u32 words);
u32 get_rand_buffer(u8 *rand, u32 bytes, GET_RAND_WORDS get_rand_words);
#endif
#endif

12
bsp/artinchip/include/hal/hal_wri.h
View File

@@ -31,16 +31,20 @@ enum aic_warm_reset_type {
WRI_TYPE_RTC_POR,
WRI_TYPE_PIN_RST,
WRI_TYPE_THS_RST,
WRI_TYPE_SP_WDOG_RST,
WRI_TYPE_SP_WDOG_SYS_RST,
WRI_TYPE_SP_WDOG_CPU_RST,
WRI_TYPE_SP_DM_NDM_RST,
WRI_TYPE_SP_DM_CPU_RST,
WRI_TYPE_CS_WDOG_RST,
WRI_TYPE_CS_WDOG_SYS_RST,
WRI_TYPE_CS_WDOG_CPU_RST,
WRI_TYPE_CS_DM_NDM_RST,
WRI_TYPE_CS_DM_CPU_RST,
WRI_TYPE_SC_WDOG_RST,
WRI_TYPE_SC_WDOG_SYS_RST,
WRI_TYPE_SC_WDOG_CPU_RST,
WRI_TYPE_SC_DM_NDM_RST,
WRI_TYPE_SC_DM_CPU_RST,
WRI_TYPE_SE_WDOG_RST,
WRI_TYPE_SE_WDOG_SYS_RST,
WRI_TYPE_SE_WDOG_CPU_RST,
WRI_TYPE_SE_DM_NDM_RST,
WRI_TYPE_MAX
};

2
bsp/artinchip/include/hal/hal_xspi.h
View File

@@ -109,6 +109,7 @@ struct hal_xspi_state {
int hal_xspi_init(hal_xspi_handle *h, struct hal_xspi_config *cfg);
int hal_xspi_reset_clk(hal_xspi_handle *h, u32 reset_clock);
int hal_xspi_set_cmd_width(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 lines);
int hal_xspi_set_cmd_width(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 lines);
int hal_xspi_set_cmd(hal_xspi_handle *h, u8 ddr_sdr_mode, u8 cmd);
@@ -128,6 +129,7 @@ int hal_xspi_set_phase_sel(hal_xspi_handle *h, u8 sel, u8 phase_sel);
int hal_xspi_set_cs(hal_xspi_handle *h, u8 sel);
int hal_xspi_set_boudary(hal_xspi_handle *h, u8 by);
int hal_xspi_set_parallel_mode(hal_xspi_handle *h, u8 mode);
int hal_xspi_set_timeout(hal_xspi_handle *h, u32 timeout);
#ifdef __cplusplus
}

138
bsp/artinchip/include/hal/hash.h Normal file
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@@ -0,0 +1,138 @@
#ifndef HASH_H
#define HASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_hash.h>
//HASH status
typedef struct {
u32 busy : 1; // calculate busy flag
} hash_status_t;
//HASH context
typedef struct
{
#ifdef AIC_HASH_MUL_THREAD
u32 iterator[HASH_ITERATOR_MAX_WORD_LEN]; //keep current hash iterator value for multiple thread
#endif
u8 hash_buffer[HASH_BLOCK_MAX_BYTE_LEN]; //block buffer
u32 total[HASH_TOTAL_LEN_MAX_WORD_LEN]; //total byte length of the whole message
hash_status_t status; //hash update status, .busy=1 means doing, .busy=0 means idle
HASH_ALG hash_alg; //current hash algorithm
u8 block_byte_len;
u8 iterator_word_len;
u8 digest_byte_len;
u8 first_update_flag; //whether first time to update message(1:yes, 0:no)
u8 finish_flag; //whether the whole message has been inputted(1:yes, 0:no)
} HASH_CTX;
#ifdef AIC_HASH_DMA
//HASH DMA context
typedef struct
{
#ifdef AIC_HASH_MUL_THREAD
u32 iterator[HASH_ITERATOR_MAX_WORD_LEN]; //keep current hash iterator value for multiple thread
#endif
u32 total[HASH_TOTAL_LEN_MAX_WORD_LEN]; //total byte length of the whole message
HASH_CALLBACK callback;
HASH_ALG hash_alg; //current hash algorithm
u8 block_word_len;
#ifdef AIC_HASH_MUL_THREAD
u8 iterator_word_len;
u8 first_update_flag; //whether first time to update message(1:yes, 0:no)
#endif
u8 digest_byte_len; //just for hmac
} HASH_DMA_CTX;
#endif
#ifdef AIC_HASH_NODE
typedef struct {
u8 *msg_addr;
u32 msg_bytes;
} HASH_NODE;
#endif
#ifdef AIC_HASH_DMA_NODE
typedef struct {
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 msg_addr_h;
u32 msg_addr_l;
#else
u32 *msg_addr;
#endif
u32 msg_bytes;
} HASH_DMA_NODE;
#endif
//APIs
u32 check_hash_alg(HASH_ALG hash_alg);
u8 hash_get_block_word_len(HASH_ALG hash_alg);
u8 hash_get_iterator_word_len(HASH_ALG hash_alg);
u8 hash_get_digest_word_len(HASH_ALG hash_alg);
u32 *hash_get_IV(HASH_ALG hash_alg);
void hash_set_IV(HASH_ALG hash_alg, u32 hash_iterator_words);
u32 hash_total_byte_len_add_uint32(u32 *a, u32 a_words, u32 b);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 hash_addr64_add_uint32(u32 *addr_h, u32 *addr_l, u32 offset);
#endif
//void hash_total_bytelen_2_bitlen(u32 *a, u32 a_words);
void hash_start_calculate(HASH_CTX *ctx);
void hash_calc_blocks(HASH_CTX *ctx, const u8 *msg, u32 block_count);
void hash_calc_rand_len_msg(HASH_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 hash_init_with_iv_and_updated_length(HASH_CTX *ctx, HASH_ALG hash_alg, u32 *iv,
u32 byte_length_h, u32 byte_length_l);
u32 hash_init(HASH_CTX *ctx, HASH_ALG hash_alg);
u32 hash_update(HASH_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 hash_final(HASH_CTX *ctx, u8 *digest);
u32 hash(HASH_ALG hash_alg, u8 *msg, u32 msg_bytes, u8 *digest);
#ifdef AIC_HASH_NODE
u32 hash_node_steps(HASH_ALG hash_alg, HASH_NODE *node, u32 node_num, u8 *digest);
#endif
#ifdef AIC_HASH_DMA
u32 hash_dma_init_with_iv_and_updated_length(HASH_DMA_CTX *ctx, HASH_ALG hash_alg, u32 *iv,
u32 byte_length_h, u32 byte_length_l, HASH_CALLBACK callback);
u32 hash_dma_init(HASH_DMA_CTX *ctx, HASH_ALG hash_alg, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 hash_dma_update_blocks(HASH_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 hash_dma_final(HASH_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 digest_h, u32 digest_l);
u32 hash_dma(HASH_ALG hash_alg, u32 msg_h, u32 msg_l, u32 msg_bytes, u32 digest_h,
u32 digest_l, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hash_dma_node_steps(HASH_ALG hash_alg, HASH_DMA_NODE *node, u32 node_num, u32 digest_h,
u32 digest_l, HASH_CALLBACK callback);
#endif
#else
u32 hash_dma_update_blocks(HASH_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 hash_dma_final(HASH_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes, u32 *digest);
u32 hash_dma(HASH_ALG hash_alg, u32 *msg, u32 msg_bytes, u32 *digest, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hash_dma_node_steps(HASH_ALG hash_alg, HASH_DMA_NODE *node, u32 node_num, u32 *digest,
HASH_CALLBACK callback);
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

36
bsp/artinchip/include/hal/hash_kdf.h Normal file
View File

@@ -0,0 +1,36 @@
#ifndef HASH_KDF_H
#define HASH_KDF_H
#include <hmac.h>
#ifdef __cplusplus
extern "C" {
#endif
//APIs
#ifdef AIC_HASH_PBKDF2
void pbkdf2_hmac_backup(HMAC_CTX *ctx_bak, HMAC_CTX *ctx);
void pbkdf2_hmac_recover(HMAC_CTX *ctx, HMAC_CTX *ctx_bak);
u32 pbkdf2_hmac(HASH_ALG hash_alg, u8 *pwd, u16 sp_key_idx, u32 pwd_bytes,
u8 *salt, u32 salt_bytes, u32 iter, u8 *out, u32 out_bytes);
#endif
#ifdef AIC_HASH_ANSI_X9_63_KDF
#ifdef AIC_HASH_NODE
u32 ansi_x9_63_kdf_node_with_xor_in(HASH_ALG hash_alg, HASH_NODE *hash_node, u32 node_num,
u32 counter_idx, u8 *in, u8 *out, u32 out_bytes, u32 check_whether_zero);
u32 ansi_x9_63_kdf_internal(HASH_ALG hash_alg, HASH_NODE *hash_node, u32 node_num,
u32 counter_idx, u8 *key, u32 key_bytes);
u32 ansi_x9_63_kdf_node(HASH_ALG hash_alg, HASH_NODE *hash_node, u32 node_num, u32 counter_idx,
u8 *k1, u32 k1_bytes, u8 *k2, u32 k2_bytes);
u32 ansi_x9_63_kdf(HASH_ALG hash_alg, u8 *Z, u32 Z_bytes, u8 *shared_info,
u32 shared_info_bytes, u8 *k1, u32 k1_bytes, u8 *k2, u32 k2_bytes);
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

75
bsp/artinchip/include/hal/hmac.h Normal file
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#ifndef HMAC_H
#define HMAC_H
#ifdef __cplusplus
extern "C" {
#endif
#include <hash.h>
#define HMAC_IPAD (0x36363636U)
#define HMAC_OPAD (0x5c5c5c5cU)
#define HMAC_IPAD_XOR_OPAD (HMAC_IPAD ^ HMAC_OPAD)
//HMAC context
typedef struct
{
u32 K0[HASH_BLOCK_MAX_WORD_LEN];
HASH_CTX hash_ctx[1];
} HMAC_CTX;
//HMAC DMA context
#ifdef AIC_HASH_DMA
typedef struct
{
u32 K0[HASH_BLOCK_MAX_WORD_LEN];
HASH_DMA_CTX hash_dma_ctx[1];
} HMAC_DMA_CTX;
#endif
//APIs
u32 hmac_init(HMAC_CTX *ctx, HASH_ALG hash_alg, const u8 *key, u16 sp_key_idx, u32 key_bytes);
u32 hmac_update(HMAC_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 hmac_final(HMAC_CTX *ctx, u8 *mac);
u32 hmac(HASH_ALG hash_alg, u8 *key, u16 sp_key_idx, u32 key_bytes, u8 *msg,
u32 msg_bytes, u8 *mac);
#ifdef AIC_HASH_NODE
u32 hmac_node_steps(HASH_ALG hash_alg, u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_NODE *node, u32 node_num, u8 *mac);
#endif
#ifdef AIC_HASH_DMA
u32 hmac_dma_init(HMAC_DMA_CTX *ctx, HASH_ALG hash_alg, const u8 *key, u16 sp_key_idx,
u32 key_bytes, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 hmac_dma_update_blocks(HMAC_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 hmac_dma_final(HMAC_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 mac_h, u32 mac_l);
u32 hmac_dma(HASH_ALG hash_alg, u8 *key, u16 sp_key_idx, u32 key_bytes, u32 msg_h,
u32 msg_l, u32 msg_bytes, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_dma_node_steps(HASH_ALG hash_alg, u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#endif
#else
u32 hmac_dma_update_blocks(HMAC_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 hmac_dma_final(HMAC_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes, u32 *mac);
u32 hmac_dma(HASH_ALG hash_alg, u8 *key, u16 sp_key_idx, u32 key_bytes, u32 *msg,
u32 msg_bytes, u32 *mac, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_dma_node_steps(HASH_ALG hash_alg, u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 *mac, HASH_CALLBACK callback);
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

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#ifndef HMAC_SHA1_H
#define HMAC_SHA1_H
#include <hmac.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SHA1_SUPPORT
typedef HMAC_CTX HMAC_SHA1_CTX;
#ifdef AIC_HASH_DMA
typedef HMAC_DMA_CTX HMAC_SHA1_DMA_CTX;
#endif
//APIs
u32 hmac_sha1_init(HMAC_SHA1_CTX *ctx, const u8 *key, u16 sp_key_idx, u32 key_bytes);
u32 hmac_sha1_update(HMAC_SHA1_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 hmac_sha1_final(HMAC_SHA1_CTX *ctx, u8 *mac);
u32 hmac_sha1(u8 *key, u16 sp_key_idx, u32 key_bytes, u8 *msg,
u32 msg_bytes, u8 *mac);
#ifdef AIC_HASH_NODE
u32 hmac_sha1_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_NODE *node, u32 node_num, u8 *mac);
#endif
#ifdef AIC_HASH_DMA
u32 hmac_sha1_dma_init(HMAC_SHA1_DMA_CTX *ctx, const u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 hmac_sha1_dma_update_blocks(HMAC_SHA1_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 hmac_sha1_dma_final(HMAC_SHA1_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 mac_h, u32 mac_l);
u32 hmac_sha1_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 msg_h, u32 msg_l,
u32 msg_bytes, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sha1_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#endif
#else
u32 hmac_sha1_dma_update_blocks(HMAC_SHA1_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 hmac_sha1_dma_final(HMAC_SHA1_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes,
u32 *mac);
u32 hmac_sha1_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 *msg,
u32 msg_bytes, u32 *mac, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sha1_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 *mac, HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

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#ifndef HMAC_SHA224_H
#define HMAC_SHA224_H
#include <hmac.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SHA224_SUPPORT
typedef HMAC_CTX HMAC_SHA224_CTX;
#ifdef AIC_HASH_DMA
typedef HMAC_DMA_CTX HMAC_SHA224_DMA_CTX;
#endif
//APIs
u32 hmac_sha224_init(HMAC_SHA224_CTX *ctx, const u8 *key, u16 sp_key_idx, u32 key_bytes);
u32 hmac_sha224_update(HMAC_SHA224_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 hmac_sha224_final(HMAC_SHA224_CTX *ctx, u8 *mac);
u32 hmac_sha224(u8 *key, u16 sp_key_idx, u32 key_bytes, u8 *msg,
u32 msg_bytes, u8 *mac);
#ifdef AIC_HASH_NODE
u32 hmac_sha224_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_NODE *node, u32 node_num, u8 *mac);
#endif
#ifdef AIC_HASH_DMA
u32 hmac_sha224_dma_init(HMAC_SHA224_DMA_CTX *ctx, const u8 *key, u16 sp_key_idx,
u32 key_bytes, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 hmac_sha224_dma_update_blocks(HMAC_SHA224_DMA_CTX *ctx, u32 msg_h, u32 msg_l,
u32 msg_bytes);
u32 hmac_sha224_dma_final(HMAC_SHA224_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 mac_h, u32 mac_l);
u32 hmac_sha224_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 msg_h,
u32 msg_l, u32 msg_bytes, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sha224_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#endif
#else
u32 hmac_sha224_dma_update_blocks(HMAC_SHA224_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 hmac_sha224_dma_final(HMAC_SHA224_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes,
u32 *mac);
u32 hmac_sha224_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 *msg,
u32 msg_bytes, u32 *mac, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sha224_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 *mac, HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

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bsp/artinchip/include/hal/hmac_sha256.h Normal file
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#ifndef HMAC_SHA256_H
#define HMAC_SHA256_H
#include <hmac.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SHA256_SUPPORT
typedef HMAC_CTX HMAC_SHA256_CTX;
#ifdef AIC_HASH_DMA
typedef HMAC_DMA_CTX HMAC_SHA256_DMA_CTX;
#endif
//APIs
u32 hmac_sha256_init(HMAC_SHA256_CTX *ctx, const u8 *key, u16 sp_key_idx, u32 key_bytes);
u32 hmac_sha256_update(HMAC_SHA256_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 hmac_sha256_final(HMAC_SHA256_CTX *ctx, u8 *mac);
u32 hmac_sha256(u8 *key, u16 sp_key_idx, u32 key_bytes, u8 *msg,
u32 msg_bytes, u8 *mac);
#ifdef AIC_HASH_NODE
u32 hmac_sha256_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_NODE *node, u32 node_num, u8 *mac);
#endif
#ifdef AIC_HASH_DMA
u32 hmac_sha256_dma_init(HMAC_SHA256_DMA_CTX *ctx, const u8 *key, u16 sp_key_idx,
u32 key_bytes, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 hmac_sha256_dma_update_blocks(HMAC_SHA256_DMA_CTX *ctx, u32 msg_h, u32 msg_l,
u32 msg_bytes);
u32 hmac_sha256_dma_final(HMAC_SHA256_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 mac_h, u32 mac_l);
u32 hmac_sha256_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 msg_h,
u32 msg_l, u32 msg_bytes, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sha256_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#endif
#else
u32 hmac_sha256_dma_update_blocks(HMAC_SHA256_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 hmac_sha256_dma_final(HMAC_SHA256_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes,
u32 *mac);
u32 hmac_sha256_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 *msg,
u32 msg_bytes, u32 *mac, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sha256_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 *mac, HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

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bsp/artinchip/include/hal/hmac_sm3.h Normal file
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#ifndef HMAC_SM3_H
#define HMAC_SM3_H
#include <hmac.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SM3_SUPPORT
typedef HMAC_CTX HMAC_SM3_CTX;
#ifdef AIC_HASH_DMA
typedef HMAC_DMA_CTX HMAC_SM3_DMA_CTX;
#endif
//APIs
u32 hmac_sm3_init(HMAC_SM3_CTX *ctx, const u8 *key, u16 sp_key_idx, u32 key_bytes);
u32 hmac_sm3_update(HMAC_SM3_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 hmac_sm3_final(HMAC_SM3_CTX *ctx, u8 *mac);
u32 hmac_sm3(u8 *key, u16 sp_key_idx, u32 key_bytes, u8 *msg,
u32 msg_bytes, u8 *mac);
#ifdef AIC_HASH_NODE
u32 hmac_sm3_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_NODE *node, u32 node_num, u8 *mac);
#endif
#ifdef AIC_HASH_DMA
u32 hmac_sm3_dma_init(HMAC_SM3_DMA_CTX *ctx, const u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 hmac_sm3_dma_update_blocks(HMAC_SM3_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 hmac_sm3_dma_final(HMAC_SM3_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 mac_h, u32 mac_l);
u32 hmac_sm3_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 msg_h, u32 msg_l,
u32 msg_bytes, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sm3_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 mac_h, u32 mac_l, HASH_CALLBACK callback);
#endif
#else
u32 hmac_sm3_dma_update_blocks(HMAC_SM3_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 hmac_sm3_dma_final(HMAC_SM3_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes,
u32 *mac);
u32 hmac_sm3_dma(u8 *key, u16 sp_key_idx, u32 key_bytes, u32 *msg, u32 msg_bytes,
u32 *mac, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 hmac_sm3_dma_node_steps(u8 *key, u16 sp_key_idx, u32 key_bytes,
HASH_DMA_NODE *node, u32 node_num, u32 *mac, HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

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bsp/artinchip/include/hal/pke_common.h Normal file
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#ifndef PKE_COMMON_H
#define PKE_COMMON_H
#include <aic_common.h>
//ECC point conversion form
#define POINT_COMPRESSED (0x02) //pc||x, pc = 0x02|LSB(y)
#define POINT_UNCOMPRESSED (0x04) //pc||x||y, pc=0x04
typedef u8 EC_POINT_FORM;
//define KDF
typedef void *(*KDF_FUNC)(const void *input, u32 byteLen, u8 *key, u32 keyByteLen);
//APIs
void pke_load_operand(u32 *baseaddr, u32 *data, u32 wordLen);
void pke_read_operand(u32 *baseaddr, u32 *data, u32 wordLen);
void pke_load_operand_U8(u32 *baseaddr, u8 *data, u32 byteLen);
void pke_read_operand_U8(u32 *baseaddr, u8 *data, u32 byteLen);
void pke_set_operand_uint32_value(u32 *baseaddr, u32 wordLen, u32 b);
#endif

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#ifndef PKE_PRIME_H
#define PKE_PRIME_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
//1:use hardware; 2:use software
#define BIGINT_DIV_CHOICE (2)
#if (BIGINT_DIV_CHOICE == 1)
typedef struct {
u32 low;
u32 high;
}double_u32;
#elif (BIGINT_DIV_CHOICE == 2)
typedef u32 double_u32;
//#define BIGINT_DIV_UINT32
#endif
//1:use Fermat primality test; 2:use Miller–Rabin primality test
#define PRIMALITY_TEST_CHOICE (1)
#if (PRIMALITY_TEST_CHOICE == 1)
#define FERMAT_ROUND (3)
#elif (PRIMALITY_TEST_CHOICE == 2)
#define MILLER_RABIN_ROUND (3)
#endif
//prime table level(total number of small prime numbers)
#define PTL_MAX (400) //the max PTL value
#define PTL_512 (400) //the best PTL value for prime bit length 512 (RSA1024)
#define PTL_1024 (400) //the best PTL value for prime bit length 1024 (RSA2048)
#define NOT_PRIME (0xFFFFFFFF)
#define MAYBE_PRIME (0)
u32 get_prime(u32 p[], u32 pBitLen);
#ifdef __cplusplus
}
#endif
#endif

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#ifndef RSA_H
#define RSA_H
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_pke.h>
#if defined(AIC_PKE_RSASSA_PSS_SUPPORT)
#include <hash.h>
#endif
//RSA return code
#define RSA_SUCCESS PKE_SUCCESS
#define RSA_BUFFER_NULL (PKE_SUCCESS+0x30U)
#define RSA_INPUT_TOO_LONG (PKE_SUCCESS+0x31U)
#define RSA_INPUT_INVALID (PKE_SUCCESS+0x32U)
//APIs
u32 RSA_ModExp(u32 *a, u32 *e, u32 *n, u32 *out, u32 eBitLen, u32 nBitLen);
u32 RSA_CRTModExp(u32 *a, u32 *p, u32 *q, u32 *dp, u32*dq,
u32 *u, u32 *out, u32 nBitLen);
u32 RSA_GetKey(u32 *e, u32 *d, u32 *n, u32 eBitLen, u32 nBitLen);
u32 RSA_GetCRTKey(u32 *e, u32 *p, u32 *q, u32 *dp, u32 *dq, u32 *u,
u32 *n, u32 eBitLen, u32 nBitLen);
#ifdef RSA_SEC
//RSA return code(secure version)
#define RSA_SUCCESS_S (0x3AEBA318U)
#define RSA_ERROR_S (0x45DF3DAEU)
u32 RSA_ModExp_with_pub(u32 *a, u32 *e, u32 *d, u32 *n, u32 *out, u32 eBitLen, u32 nBitLen);
u32 RSA_ModExp_without_pub(u32 *a, u32 *d, u32 *n, u32 *out, u32 nBitLen);
u32 RSA_CRTModExp_with_pub(u32 *a, u32 *p, u32 *q, u32 *dp, u32*dq, u32 *u, u32 *e,
u32 *out, u32 eBitLen, u32 nBitLen);
u32 RSA_CRTModExp_without_pub(u32 *a, u32 *p, u32 *q, u32 *dp, u32*dq, u32 *u,
u32 *out, u32 nBitLen);
#endif
typedef struct {
u8 *p;
u8 *q;
u8 *dp;
u8 *dq;
u8 *u;//qinv
} RSA_CRT_PRIVATE_KEY;
#if (defined(AIC_PKE_RSASSA_PSS_SUPPORT) || defined(SUPPORT_RSAES_OAEP))
void rsa_pkcs1_mgf1_counter_add(u8 *counter, u32 bytes, u8 b);
u32 rsa_pkcs1_mgf1_with_xor_in(HASH_ALG hash_alg, u8 *seed, u32 seed_bytes, u8 *in,
u8 *out, u32 mask_bytes);
#endif
#ifdef AIC_PKE_RSASSA_PSS_SUPPORT
u32 rsa_ssa_pss_sign_by_msg_digest(HASH_ALG msg_hash_alg, HASH_ALG mgf_hash_alg, u8 *salt, u32 salt_bytes,
u8 *msg_digest, u8 *d, u8 *n, u32 n_bits, u8 *signature);
u32 rsa_ssa_pss_sign(HASH_ALG msg_hash_alg, HASH_ALG mgf_hash_alg, u8 *salt, u32 salt_bytes, u8 *msg,
u32 msg_bytes, u8 *d, u8 *n, u32 n_bits, u8 *signature);
u32 rsa_ssa_pss_crt_sign_by_msg_digest(HASH_ALG msg_hash_alg, HASH_ALG mgf_hash_alg, u8 *salt, u32 salt_bytes,
u8 *msg_digest, RSA_CRT_PRIVATE_KEY *d, u32 n_bits, u8 *signature);
u32 rsa_ssa_pss_crt_sign(HASH_ALG msg_hash_alg, HASH_ALG mgf_hash_alg, u8 *salt, u32 salt_bytes, u8 *msg,
u32 msg_bytes, RSA_CRT_PRIVATE_KEY *d, u32 n_bits, u8 *signature);
u32 rsa_ssa_pss_verify_by_msg_digest(HASH_ALG msg_hash_alg, HASH_ALG mgf_hash_alg, s32 salt_bytes,
u8 *msg_digest, u8 *e, u32 e_bits, u8 *n, u32 n_bits, u8 *signature);
u32 rsa_ssa_pss_verify(HASH_ALG msg_hash_alg, HASH_ALG mgf_hash_alg, s32 salt_bytes, u8 *msg,
u32 msg_bytes, u8 *e, u32 e_bits, u8 *n, u32 n_bits, u8 *signature);
#endif
#ifdef __cplusplus
}
#endif
#endif

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#ifndef SHA1_H
#define SHA1_H
#include <hash.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SHA1_SUPPORT
typedef HASH_CTX SHA1_CTX;
#ifdef AIC_HASH_DMA
typedef HASH_DMA_CTX SHA1_DMA_CTX;
#endif
//APIs
u32 sha1_init(SHA1_CTX *ctx);
u32 sha1_update(SHA1_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 sha1_final(SHA1_CTX *ctx, u8 *digest);
u32 sha1(u8 *msg, u32 msg_bytes, u8 *digest);
#ifdef AIC_HASH_NODE
u32 sha1_node_steps(HASH_NODE *node, u32 node_num, u8 *digest);
#endif
#ifdef AIC_HASH_DMA
u32 sha1_dma_init(SHA1_DMA_CTX *ctx, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 sha1_dma_update_blocks(SHA1_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 sha1_dma_final(SHA1_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 digest_h, u32 digest_l);
u32 sha1_dma(u32 msg_h, u32 msg_l, u32 msg_bytes, u32 digest_h, u32 digest_l,
HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sha1_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 digest_h,
u32 digest_l, HASH_CALLBACK callback);
#endif
#else
u32 sha1_dma_update_blocks(SHA1_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 sha1_dma_final(SHA1_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes, u32 *digest);
u32 sha1_dma(u32 *msg, u32 msg_bytes, u32 *digest, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sha1_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 *digest,
HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

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#ifndef SHA224_H
#define SHA224_H
#include <hash.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SHA224_SUPPORT
typedef HASH_CTX SHA224_CTX;
#ifdef AIC_HASH_DMA
typedef HASH_DMA_CTX SHA224_DMA_CTX;
#endif
//APIs
u32 sha224_init(SHA224_CTX *ctx);
u32 sha224_update(SHA224_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 sha224_final(SHA224_CTX *ctx, u8 *digest);
u32 sha224(u8 *msg, u32 msg_bytes, u8 *digest);
#ifdef AIC_HASH_NODE
u32 sha224_node_steps(HASH_NODE *node, u32 node_num, u8 *digest);
#endif
#ifdef AIC_HASH_DMA
u32 sha224_dma_init(SHA224_DMA_CTX *ctx, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 sha224_dma_update_blocks(SHA224_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 sha224_dma_final(SHA224_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 digest_h, u32 digest_l);
u32 sha224_dma(u32 msg_h, u32 msg_l, u32 msg_bytes, u32 digest_h, u32 digest_l,
HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sha224_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 digest_h,
u32 digest_l, HASH_CALLBACK callback);
#endif
#else
u32 sha224_dma_update_blocks(SHA224_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 sha224_dma_final(SHA224_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes, u32 *digest);
u32 sha224_dma(u32 *msg, u32 msg_bytes, u32 *digest, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sha224_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 *digest,
HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

59
bsp/artinchip/include/hal/sha256.h Normal file
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@@ -0,0 +1,59 @@
#ifndef SHA256_H
#define SHA256_H
#include <hash.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SHA256_SUPPORT
typedef HASH_CTX SHA256_CTX;
#ifdef AIC_HASH_DMA
typedef HASH_DMA_CTX SHA256_DMA_CTX;
#endif
//APIs
u32 sha256_init(SHA256_CTX *ctx);
u32 sha256_update(SHA256_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 sha256_final(SHA256_CTX *ctx, u8 *digest);
u32 sha256(u8 *msg, u32 msg_bytes, u8 *digest);
#ifdef AIC_HASH_NODE
u32 sha256_node_steps(HASH_NODE *node, u32 node_num, u8 *digest);
#endif
#ifdef AIC_HASH_DMA
u32 sha256_dma_init(SHA256_DMA_CTX *ctx, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 sha256_dma_update_blocks(SHA256_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 sha256_dma_final(SHA256_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 digest_h, u32 digest_l);
u32 sha256_dma(u32 msg_h, u32 msg_l, u32 msg_bytes, u32 digest_h, u32 digest_l,
HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sha256_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 digest_h,
u32 digest_l, HASH_CALLBACK callback);
#endif
#else
u32 sha256_dma_update_blocks(SHA256_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 sha256_dma_final(SHA256_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes, u32 *digest);
u32 sha256_dma(u32 *msg, u32 msg_bytes, u32 *digest, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sha256_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 *digest,
HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

33
bsp/artinchip/include/hal/ske.h Normal file
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@@ -0,0 +1,33 @@
#ifndef SKE_H
#define SKE_H
#include <hal_ske.h>
#ifdef __cplusplus
extern "C" {
#endif
//APIs
void ske_big_endian_add_uint8(u8 *a, u32 a_bytes, u8 b);
//void ske_little_endian_add_uint32(u32 *a, u32 a_words, u32 b);
u8 ske_sec_get_key_byte_len(SKE_ALG ske_alg);
u8 ske_sec_get_block_byte_len(SKE_ALG ske_alg);
void ske_set_key(SKE_ALG alg, u8 *key, u16 key_bytes, u16 key_idx);
u32 keep_alg_key_iv(SKE_CTX *ctx, SKE_ALG alg, SKE_MODE mode, u8 *key, u16 sp_key_idx, u8 *iv);
u32 ske_sec_init_internal(SKE_CTX *ctx, SKE_ALG alg, SKE_MODE mode, SKE_CRYPTO crypto, u8 *key,
u16 sp_key_idx, u8 *iv);
u32 ske_sec_init(SKE_CTX *ctx, SKE_ALG alg, SKE_MODE mode, SKE_CRYPTO crypto, u8 *key,
u16 sp_key_idx, u8 *iv, SKE_PADDING padding);
u32 ske_sec_update_blocks(SKE_CTX *ctx, u8 *in, u8 *out, u32 bytes);
u32 ske_sec_update_including_last_block(SKE_CTX *ctx, u8 *in, u8 *out, u32 in_bytes,
u32 *out_bytes);
u32 ske_sec_final(SKE_CTX *ctx);
u32 ske_sec_crypto(SKE_ALG alg, SKE_MODE mode, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx, u8 *iv,
SKE_PADDING padding, u8 *in, u8 *out, u32 in_bytes, u32 *out_bytes);
#ifdef __cplusplus
}
#endif
#endif

25
bsp/artinchip/include/hal/ske_cbc.h Normal file
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@@ -0,0 +1,25 @@
#ifndef SKE_CBC_H
#define SKE_CBC_H
#include <ske.h>
#ifdef __cplusplus
extern "C" {
#endif
//APIs
u32 ske_sec_cbc_init(SKE_CTX *ctx, SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx,
u8 *iv, SKE_PADDING padding);
u32 ske_sec_cbc_update_blocks(SKE_CTX *ctx, u8 *in, u8 *out, u32 bytes);
u32 ske_sec_cbc_update_including_last_block(SKE_CTX *ctx, u8 *in, u8 *out, u32 in_bytes,
u32 *out_bytes);
u32 ske_sec_cbc_final(SKE_CTX *ctx);
u32 ske_sec_cbc_crypto(SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx, u8 *iv,
SKE_PADDING padding, u8 *in, u8 *out, u32 in_bytes, u32 *out_bytes);
#ifdef __cplusplus
}
#endif
#endif

25
bsp/artinchip/include/hal/ske_cfb.h Normal file
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@@ -0,0 +1,25 @@
#ifndef SKE_CFB_H
#define SKE_CFB_H
#include <ske.h>
#ifdef __cplusplus
extern "C" {
#endif
//APIs
u32 ske_sec_cfb_init(SKE_CTX *ctx, SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx,
u8 *iv, SKE_PADDING padding);
u32 ske_sec_cfb_update_blocks(SKE_CTX *ctx, u8 *in, u8 *out, u32 bytes);
u32 ske_sec_cfb_update_including_last_block(SKE_CTX *ctx, u8 *in, u8 *out, u32 in_bytes,
u32 *out_bytes);
u32 ske_sec_cfb_final(SKE_CTX *ctx);
u32 ske_sec_cfb_crypto(SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx, u8 *iv,
SKE_PADDING padding, u8 *in, u8 *out, u32 in_bytes, u32 *out_bytes);
#ifdef __cplusplus
}
#endif
#endif

25
bsp/artinchip/include/hal/ske_ctr.h Normal file
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@@ -0,0 +1,25 @@
#ifndef SKE_CTR_H
#define SKE_CTR_H
#include <ske.h>
#ifdef __cplusplus
extern "C" {
#endif
//APIs
u32 ske_sec_ctr_init(SKE_CTX *ctx, SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx,
u8 *iv, SKE_PADDING padding);
u32 ske_sec_ctr_update_blocks(SKE_CTX *ctx, u8 *in, u8 *out, u32 bytes);
u32 ske_sec_ctr_update_including_last_block(SKE_CTX *ctx, u8 *in, u8 *out, u32 in_bytes,
u32 *out_bytes);
u32 ske_sec_ctr_final(SKE_CTX *ctx);
u32 ske_sec_ctr_crypto(SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx, u8 *iv,
SKE_PADDING padding, u8 *in, u8 *out, u32 in_bytes, u32 *out_bytes);
#ifdef __cplusplus
}
#endif
#endif

25
bsp/artinchip/include/hal/ske_ecb.h Normal file
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@@ -0,0 +1,25 @@
#ifndef SKE_ECB_H
#define SKE_ECB_H
#include <ske.h>
#ifdef __cplusplus
extern "C" {
#endif
//APIs
u32 ske_sec_ecb_init(SKE_CTX *ctx, SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx,
SKE_PADDING padding);
u32 ske_sec_ecb_update_blocks(SKE_CTX *ctx, u8 *in, u8 *out, u32 bytes);
u32 ske_sec_ecb_update_including_last_block(SKE_CTX *ctx, u8 *in, u8 *out, u32 in_bytes,
u32 *out_bytes);
u32 ske_sec_ecb_final(SKE_CTX *ctx);
u32 ske_sec_ecb_crypto(SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx,
SKE_PADDING padding, u8 *in, u8 *out, u32 in_bytes, u32 *out_bytes);
#ifdef __cplusplus
}
#endif
#endif

25
bsp/artinchip/include/hal/ske_ofb.h Normal file
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@@ -0,0 +1,25 @@
#ifndef SKE_OFB_H
#define SKE_OFB_H
#include <ske.h>
#ifdef __cplusplus
extern "C" {
#endif
//APIs
u32 ske_sec_ofb_init(SKE_CTX *ctx, SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx,
u8 *iv, SKE_PADDING padding);
u32 ske_sec_ofb_update_blocks(SKE_CTX *ctx, u8 *in, u8 *out, u32 bytes);
u32 ske_sec_ofb_update_including_last_block(SKE_CTX *ctx, u8 *in, u8 *out, u32 in_bytes,
u32 *out_bytes);
u32 ske_sec_ofb_final(SKE_CTX *ctx);
u32 ske_sec_ofb_crypto(SKE_ALG alg, SKE_CRYPTO crypto, u8 *key, u16 sp_key_idx, u8 *iv,
SKE_PADDING padding, u8 *in, u8 *out, u32 in_bytes, u32 *out_bytes);
#ifdef __cplusplus
}
#endif
#endif

18
bsp/artinchip/include/hal/ske_secure_port.h Normal file
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@@ -0,0 +1,18 @@
#ifndef SKE_SECURE_PORT_H
#define SKE_SECURE_PORT_H
#include <ske.h>
#ifdef __cplusplus
extern "C" {
#endif
void ske_sec_enable_secure_port(u16 sp_key_idx);
void ske_sec_disable_secure_port(void);
#ifdef __cplusplus
}
#endif
#endif

94
bsp/artinchip/include/hal/sm2.h Normal file
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@@ -0,0 +1,94 @@
#ifndef SM2_H
#define SM2_H
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_pke.h>
#include <hash.h>
#if (defined(PKE_HP) || defined(PKE_UHP))
#define SM2_HIGH_SPEED //only available for PKE_HP, PKE_UHP
#endif
//some sm2 length
#define SM3_DIGEST_BYTE_LEN SM2_BYTE_LEN
#define SM2_MAX_ID_BYTE_LEN (1<<13)
//SM2 return code
#define SM2_SUCCESS PKE_SUCCESS
#define SM2_BUFFER_NULL (PKE_SUCCESS+0x40U)
#define SM2_NOT_ON_CURVE (PKE_SUCCESS+0x41U)
#define SM2_EXCHANGE_ROLE_INVALID (PKE_SUCCESS+0x42U)
#define SM2_INPUT_INVALID (PKE_SUCCESS+0x43U)
#define SM2_ZERO_ALL (PKE_SUCCESS+0x44U)
#define SM2_INTEGER_TOO_BIG (PKE_SUCCESS+0x45U)
#define SM2_VERIFY_FAILED (PKE_SUCCESS+0x46U)
#define SM2_DECRYPT_VERIFY_FAILED (PKE_SUCCESS+0x47U)
//SM2 key exchange role
typedef enum {
SM2_Role_Sponsor = 0,
SM2_Role_Responsor
} sm2_exchange_role_e;
// SM2 ciphertext order
typedef enum {
SM2_C1C3C2 = 0,
SM2_C1C2C3,
} sm2_cipher_order_e;
//APIs
u32 sm2_getZ(u8 *ID, u32 byteLenofID, u8 pubKey[65], u8 Z[32]);
u32 sm2_getE(u8 *M, u32 byteLen, u8 Z[32], u8 E[32]);
//#define SM2_GETE_BY_STEPS
#ifdef SM2_GETE_BY_STEPS
u32 sm2_getE_init(HASH_CTX *ctx, u8 Z[32]);
u32 sm2_getE_update(HASH_CTX *ctx, u8 *msg, u32 msg_bytes);
u32 sm2_getE_final(HASH_CTX *ctx, u8 E[32]);
#endif
u32 sm2_get_pubkey_from_prikey(u8 priKey[32], u8 pubKey[65]);
u32 sm2_getkey(u8 priKey[32], u8 pubKey[65]);
u32 sm2_sign(u8 E[32], u8 rand_k[32], u8 priKey[32], u8 signature[64]);
u32 sm2_verify(u8 E[32], u8 pubKey[65], u8 signature[64]);
u32 sm2_encrypt(u8 *M, u32 MByteLen, u8 rand_k[32], u8 pubKey[65],
sm2_cipher_order_e order, u8 *C, u32 *CByteLen);
u32 sm2_decrypt(u8 *C, u32 CByteLen, u8 priKey[32],
sm2_cipher_order_e order, u8 *M, u32 *MByteLen);
u32 sm2_exchangekey(sm2_exchange_role_e role,
u8 *dA, u8 *PB,
u8 *rA, u8 *RA,
u8 *RB,
u8 *ZA, u8 *ZB,
u32 kByteLen,
u8 *KA, u8 *S1, u8 *SA);
#ifdef SM2_SEC
//SM2 return code(secure version)
#define SM2_SUCCESS_S (0x3E2FDB1AU)
#define SM2_ERROR_S (0xCBAD735EU)
u32 sm2_sign_s(u8 E[32], u8 rand_k[32], u8 priKey[32], u8 signature[64]);
u32 sm2_verify_s(u8 E[32], u8 pubKey[65], u8 signature[64]);
u32 sm2_encrypt_s(u8 *M, u32 MByteLen, u8 rand_k[32], u8 pubKey[65],
sm2_cipher_order_e order, u8 *C, u32 *CByteLen);
u32 sm2_decrypt_s(u8 *C, u32 CByteLen, u8 priKey[32],
sm2_cipher_order_e order, u8 *M, u32 *MByteLen);
u32 sm2_exchangekey_s(sm2_exchange_role_e role,
u8 *dA, u8 *PB,
u8 *rA, u8 *RA,
u8 *RB,
u8 *ZA, u8 *ZB,
u32 kByteLen,
u8 *KA, u8 *S1, u8 *SA);
#endif
#ifdef __cplusplus
}
#endif
#endif

61
bsp/artinchip/include/hal/sm3.h Normal file
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@@ -0,0 +1,61 @@
#ifndef SM3_H
#define SM3_H
#include <hash.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AIC_HASH_SM3_SUPPORT
typedef HASH_CTX SM3_CTX;
#ifdef AIC_HASH_DMA
typedef HASH_DMA_CTX SM3_DMA_CTX;
#endif
//APIs
u32 sm3_init(SM3_CTX *ctx);
u32 sm3_update(SM3_CTX *ctx, const u8 *msg, u32 msg_bytes);
u32 sm3_final(SM3_CTX *ctx, u8 *digest);
u32 sm3(u8 *msg, u32 msg_bytes, u8 *digest);
#ifdef AIC_HASH_NODE
u32 sm3_node_steps(HASH_NODE *node, u32 node_num, u8 *digest);
#endif
#ifdef AIC_HASH_DMA
u32 sm3_dma_init(SM3_DMA_CTX *ctx, HASH_CALLBACK callback);
#ifdef AIC_HASH_ADDRESS_HIGH_LOW
u32 sm3_dma_update_blocks(SM3_DMA_CTX *ctx, u32 msg_h, u32 msg_l, u32 msg_bytes);
u32 sm3_dma_final(SM3_DMA_CTX *ctx, u32 remainder_msg_h, u32 remainder_msg_l,
u32 remainder_bytes, u32 digest_h, u32 digest_l);
u32 sm3_dma(u32 msg_h, u32 msg_l, u32 msg_bytes, u32 digest_h, u32 digest_l,
HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sm3_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 digest_h, u32 digest_l,
HASH_CALLBACK callback);
#endif
#else
u32 sm3_dma_update_blocks(SM3_DMA_CTX *ctx, u32 *msg, u32 msg_bytes);
u32 sm3_dma_final(SM3_DMA_CTX *ctx, u32 *remainder_msg, u32 remainder_bytes, u32 *digest);
u32 sm3_dma(u32 *msg, u32 msg_bytes, u32 *digest, HASH_CALLBACK callback);
#ifdef AIC_HASH_DMA_NODE
u32 sm3_dma_node_steps(HASH_DMA_NODE *node, u32 node_num, u32 *digest,
HASH_CALLBACK callback);
#endif
#endif
#endif
#endif
#ifdef __cplusplus
}
#endif
#endif

21
bsp/artinchip/include/hal/trng.h Normal file
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@@ -0,0 +1,21 @@
#ifndef TRNG_H
#define TRNG_H
#include <hal_trng.h>
#ifdef __cplusplus
extern "C" {
#endif
u32 get_rand_internal(u8 *a, u32 bytes);
u32 get_rand_fast(u8 *rand, u32 bytes);
#ifndef AIC_TRNG_GENERATE_BY_HARDWARE
u32 get_rand_register(void);
#endif
u32 get_rand(u8 *rand, u32 bytes);
#ifdef __cplusplus
}
#endif
#endif

56
bsp/artinchip/include/hal/utility.h Normal file
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@@ -0,0 +1,56 @@
#ifndef UTILITY_H
#define UTILITY_H
#ifdef __cplusplus
extern "C" {
#endif
#include <aic_common.h>
#define CAST2UINT32(a) ((u32)(a))
#define GET_MAX_LEN(a,b) (((a)>(b))?(a):(b))
#define GET_MIN_LEN(a,b) (((a)>(b))?(b):(a))
#define GET_WORD_LEN(bitLen) (((bitLen)+31)/32)
#define GET_BYTE_LEN(bitLen) (((bitLen)+7)/8)
//APIs
#ifdef AIC_UTILITY_PRINT_BUF
extern void print_buf_U8(u8 *buf, u32 byteLen, char *name);
extern void print_buf_U32(u32 *buf, u32 wordLen, char *name);
extern void print_BN_buf_U32(u32 *buf, u32 wordLen, char *name);
#endif
void memcpy_(u8 *dst, u8 *src, u32 size);
void memset_(u8 *dst, u8 value, u32 size);
u8 memcmp_(u8 *m1, u8 *m2, u32 size);
void uint32_set(u32 *a, u32 value, u32 wordLen);
void uint32_copy(u32 *dst, u32 *src, u32 wordLen);
void uint32_clear(u32 *a, u32 wordLen);
void uint32_sleep(u32 count, u8 rand);
void uint32_endian_reverse(u8 *in, u8 *out, u32 wordLen);
void reverse_byte_array(u8 *in, u8 *out, u32 byteLen);
//void reverse_word(u8 *in, u8 *out, u32 bytelen);
//void dma_reverse_word_array(u32 *in, u32 *out, u32 wordlen, u32 reverse_word);
void uint8_XOR(u8 *A, u8 *B, u8 *C, u32 byteLen);
void uint32_XOR(u32 *A, u32 *B, u32 *C, u32 wordLen);
u32 get_bit_value_by_index(const u32 *a, u32 bit_index);
u32 get_valid_bits(const u32 *a, u32 wordLen);
u32 get_valid_words(u32 *a, u32 max_words);
u8 uint8_BigNum_Check_Zero(u8 *a, u32 aByteLen);
u32 uint32_BigNum_Check_Zero(u32 *a, u32 aWordLen);
u32 uint8_big_num_big_endian_add_little(u8 *a, u32 a_bytes, u8 b, u8 is_secure);
u32 uint32_big_num_little_endian_add_little(u32 *a, u32 a_words, u32 b, u8 is_secure);
int uint32_BigNumCmp(u32 *a, u32 aWordLen, u32 *b, u32 bWordLen);
u32 Get_Multiple2_Number(u32 *a);
u32 Big_Div2n(u32 *a, u32 aWordLen, u32 n);
u8 Bigint_Check_1(u32 *a, u32 aWordLen);
u8 Bigint_Check_p_1(u32 *a, u32 *p, u32 wordLen);
u32 uint32_integer_check(u32 *k, u32 *n, u32 wordLen, u32 ret_zero, u32 ret_big, u32 ret_success);
#ifdef __cplusplus
}
#endif
#endif

24
bsp/artinchip/include/hal/utility_sec.h Normal file
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@@ -0,0 +1,24 @@
#ifndef UTILITY_SEC_H
#define UTILITY_SEC_H
#include "utility.h"
#ifdef __cplusplus
extern "C" {
#endif
u16 crc16_calc(u8 *in, u32 bytelen, u16 crc);
u32 uint32_get_rand_big_number_msb_0(u32 *a, u32 aBitLen);
u8 uint8_BigNum_Check_Zero_sec(u8 a[], u32 aByteLen);
u32 uint32_BigNum_Check_Zero_sec(u32 a[], u32 aWordLen);
int uint32_BigNumCmp_sec(u32 *a, u32 aWordLen, u32 *b, u32 bWordLen);
u32 uint32_cmp_sec(u32 *a, u32 *b, u32 wordLen, u8 rand);
u32 uint32_integer_check_sec(u32 *k, u32 *n, u32 wordLen, u32 ret_zero, u32 ret_big,
u32 ret_success);
#ifdef __cplusplus
}
#endif
#endif

3
bsp/artinchip/include/uapi/artinchip_fb.h
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@@ -292,6 +292,9 @@ struct aicfb_screeninfo {
/** get gamma config */
#define AICFB_GET_GAMMA_CONFIG _IOR(IOC_TYPE_FB, 0x68, struct aicfb_gamma_config)
/* get screen register value */
#define AICFB_GET_SCREENREG _IOR(IOC_TYPE_FB, 0x69, unsigned int)
/* get screen info */
#define AICFB_GET_SCREENINFO _IOR(IOC_TYPE_FB, 0x62, struct aicfb_screeninfo)