v1.0.3

bsp/artinchip/include/drv_bare/block_dev.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2024, Artinchip Technology Co., Ltd
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Wudehuang <dehuang.wu@artinchip.com>
+ */
+
+#ifndef __AIC_BLOCK_DEV_H_
+#define __AIC_BLOCK_DEV_H_
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <aic_common.h>
+#include <aic_list.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct block_dev;
+struct block_drv_ops {
+    u32 (*read)(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
+    u32 (*write)(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
+};
+
+struct block_dev {
+    struct list_head list;
+    char *name;
+    struct block_dev *parent;
+    /* Partition Offset in parent device, it should be 0 if it is root device */
+    u32 blk_offset;
+    u32 blk_size;
+    u32 blk_cnt;
+    struct block_drv_ops ops;
+    void *priv;
+};
+
+int block_add_device(struct block_dev *dev);
+int block_del_device(struct block_dev *dev);
+u32 block_get_device_count(void);
+struct block_dev *block_get_device_by_id(u32 id);
+struct block_dev *block_get_device(const char *name);
+u32 block_read(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
+u32 block_write(struct block_dev *dev, u32 start_blk, u32 blkcnt, u8 *data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AIC_BLOCK_DEV_H_ */

bsp/artinchip/include/drv_bare/mmc.h

@@ -11,6 +11,7 @@
 
 #include <aic_core.h>
 #include <hal_sdmc.h>
+#include <aic_partition.h>
 
 struct aic_sdmc_pdata {
     ulong base;
@@ -18,7 +19,7 @@ struct aic_sdmc_pdata {
     int clk;
     u32 is_sdio;
     u8 id;
-    u8 buswidth8;
+    u8 buswidth;
     u8 drv_phase;
     u8 smp_phase;
 };
@@ -33,7 +34,7 @@ struct aic_sdmc_dev {
     u32 bus_width;
     u32 clock;
     u32 card_caps;
-    u32 card_capacity;
+    u32 card_capacity; /* unit: KB*/
     u32 host_caps;
     u32 valid_ocr;
     u32 scr[2];
@@ -42,6 +43,7 @@ struct aic_sdmc_dev {
     u32 boot_bus_cond;
     u32 part_num;
     u32 read_bl_len;
+    u32 erase_grp_size; /* in 512-byte sectors */
     u32 blk_max;
     u32 sdmc_id;
     u32 max_seg_size;
@@ -69,13 +71,6 @@ struct aic_sdmc_data {
     int err;
 };
 
-struct aic_partition {
-    char name[32];
-    u64 start;
-    u64 size;
-    struct aic_partition *next;
-};
-
 /**
  * struct aic_sdmc - Information about a ArtInChip SDMC host
  *
@@ -102,7 +97,6 @@ struct aic_sdmc {
     unsigned int clock;
     unsigned int sclk_rate;
     unsigned int div;
-    int buswidth;
     int ddr_mode;
 
     /* use fifo mode to read and write data */
@@ -199,7 +193,8 @@ struct aic_sdmc {
 #define OCR_VOLTAGE_MASK 0x00FFFF80
 #define OCR_ACCESS_MODE  0x60000000
 
-#define SECURE_ERASE 0x80000000
+#define MMC_ERASE_ARG    0x00000000
+#define MMC_SECURE_ERASE 0x80000000
 
 #define MMC_STATUS_MASK         (~0x0206BF7F)
 #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
@@ -321,10 +316,15 @@ s32 mmc_init(int id);
 s32 mmc_deinit(int id);
 u32 mmc_bread(void *priv, u32 start, u32 blkcnt, u8 *dst);
 u32 mmc_bwrite(struct aic_sdmc *host, u32 start, u32 blkcnt, const u8 *src);
+u32 mmc_berase(struct aic_sdmc *host, u32 start, u32 blkcnt);
 struct aic_sdmc *find_mmc_dev_by_index(int id);
 struct aic_partition *mmc_new_partition(char *s, u64 start);
 void mmc_free_partition(struct aic_partition *part);
 struct aic_partition *mmc_create_gpt_part(void);
 void sdcard_hotplug_init(void);
+int mmc_block_init(struct aic_sdmc *host);
+int mmc_block_refresh(struct aic_sdmc *host);
+int mmc_block_deinit(struct aic_sdmc *host);
+
 
 #endif /* _AIC_MMC_H_ */

bsp/artinchip/include/drv_bare/mtd.h

@@ -16,12 +16,32 @@
 extern "C" {
 #endif
 
+#define MAX_NAND_NAME 32
+struct nftl_volume {
+    char name[MAX_NAND_NAME];
+    int vol_type;
+    u32 size;
+    struct nftl_volume *next;
+};
+
+struct nftl_mtd {
+    char name[MAX_NAND_NAME];
+    struct nftl_mtd *next;
+    struct nftl_volume *vols;
+};
+
+enum part_attr {
+    PART_ATTR_MTD = 0,
+    PART_ATTR_NFTL,
+};
+
 #define MAX_MTD_NAME 64
 struct mtd_partition {
     char name[MAX_MTD_NAME];
     u32 start;
     u32 size;
     struct mtd_partition *next;
+    enum part_attr attr;
 };
 
 struct mtd_dev;
@@ -48,6 +68,7 @@ struct mtd_dev {
     unsigned long oobsize;
     struct mtd_drv_ops ops;
     void *priv;
+    enum part_attr attr;
 };
 
 int mtd_probe(void);
@@ -69,6 +90,10 @@ struct mtd_partition *mtd_parts_parse(char *parts);
 void mtd_parts_free(struct mtd_partition *head);
 int mtd_contread(struct mtd_dev *mtd, u32 offset, u8 *data, u32 len);
 
+struct nftl_mtd *build_nftl_list(char *nftlvols);
+void free_nftl_list(struct nftl_mtd *nftl);
+u8 partition_nftl_is_exist(char *mtd_name, struct nftl_mtd *nftl_list);
+
 #ifdef __cplusplus
 }
 #endif

bsp/artinchip/include/drv_bare/xspi_psram.h

@@ -26,6 +26,9 @@ struct aic_xspi
     bool inited;
 };
 
+#define PSRAM_INIT_OK 0
+#define PSRAM_INIT_FAILED 1
+
 u32 aic_xspi_psram_init(void);
 
 #ifdef __cplusplus