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v1.0.3

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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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25
bsp/artinchip/include/hal/aic_hal_clk_cmu.h
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@@ -13,6 +13,8 @@ extern "C" {
struct aic_clk_comm_cfg {
struct aic_clk_ops *ops;
const char *name;
bool enable_count;
};
struct aic_clk_fixed_rate_cfg {
@@ -79,6 +81,7 @@ struct aic_clk_multi_parent_cfg {
struct aic_clk_cpu_cfg {
struct aic_clk_comm_cfg comm;
u32 offset_reg;
u32 key_val;
u8 key_bit;
u8 key_mask;
s32 gate_bit;
@@ -145,12 +148,14 @@ struct aic_clk_ops {
.id = _id, \
.parent_id = 0, \
.rate = _rate, \
.comm.enable_count = 1, \
.comm.ops = &aic_clk_fixed_rate_ops, \
.comm.name = _name, \
}
#define FRCLK(_id, _name, _rate) FRCLK_DEF(_id, _name, _rate)
/* For PLL clock */
#define PLL_DEF(_id, _type, _parent_id, _gen, _fra, _sdm, _flag) \
#define PLL_DEF(_id, _name, _type, _parent_id, _gen, _fra, _sdm, _flag) \
static const struct aic_clk_pll_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_id = _parent_id, \
@@ -160,13 +165,14 @@ struct aic_clk_ops {
.offset_sdm = _sdm, \
.flag = _flag, \
.comm.ops = &aic_clk_pll_ops, \
.comm.name = _name, \
}
#define PLL_INT(_id, _name, _parent_id, _parent_name, _gen, _flag) \
PLL_DEF(_id, AIC_PLL_INT, _parent_id, _gen, 0, 0, _flag)
PLL_DEF(_id, _name, AIC_PLL_INT, _parent_id, _gen, 0, 0, _flag)
#define PLL_FRA(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
PLL_DEF(_id, AIC_PLL_FRA, _parent_id, _gen, _fra, _sdm, _flag)
PLL_DEF(_id, _name, AIC_PLL_FRA, _parent_id, _gen, _fra, _sdm, _flag)
#define PLL_SDM(_id, _name, _parent_id, _parent_name, _gen, _fra, _sdm, _flag) \
PLL_DEF(_id, AIC_PLL_SDM, _parent_id, _gen, _fra, _sdm, _flag)
PLL_DEF(_id, _name, AIC_PLL_SDM, _parent_id, _gen, _fra, _sdm, _flag)
/* For clocks fixed parent */
#define FPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _bus, _mod, \
@@ -184,6 +190,7 @@ struct aic_clk_ops {
.div_step = _step, \
.flag = _flag, \
.comm.ops = &aic_clk_fixed_parent_ops, \
.comm.name = _name, \
}
#define FPCLK(_id, _name, _parent_id, _parent_name, _reg, _bus, _mod, _div, \
_width) \
@@ -213,19 +220,21 @@ struct aic_clk_ops {
.div0_bit = _div0, \
.div0_mask = ((1 << _div0w) - 1), \
.comm.ops = &aic_clk_multi_parent_ops, \
.comm.name = _name, \
}
#define MPCLK(_id, _name, _parent, _reg, _mod, _mux, _muxw, _div0, _div0w) \
MPCLK_DEF(_id, _name, _parent, _reg, -1, _mod, _mux, _muxw, _div0, _div0w)
#define MPCLK_BUS(_id, _name, _parent, _reg, _bus, _mod, _mux, _muxw, _div0, _div0w) \
MPCLK_DEF(_id, _name, _parent, _reg, _bus, _mod, _mux, _muxw, _div0, _div0w)
#define CPUCLK_DEF(_id, _name, _parent, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, \
#define CPUCLK_DEF(_id, _name, _parent, _reg, _key_val, _key, _keyw, _gate, _mux, _muxw, _div0, \
_div0w) \
static const struct aic_clk_cpu_cfg aic_clk_cfg_##_id = { \
.id = _id, \
.parent_ids = _parent, \
.num_parents = ARRAY_SIZE(_parent), \
.offset_reg = _reg, \
.key_val = _key_val, \
.key_bit = _key, \
.key_mask = _keyw, \
.gate_bit = _gate, \
@@ -234,9 +243,10 @@ struct aic_clk_ops {
.div0_bit = _div0, \
.div0_mask = ((1 << _div0w) - 1), \
.comm.ops = &aic_clk_cpu_ops, \
.comm.name = _name, \
}
#define CPUCLK(_id, _name, _parent, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w) \
CPUCLK_DEF(_id, _name, _parent, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w)
#define CPUCLK(_id, _name, _parent, _key_val, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w) \
CPUCLK_DEF(_id, _name, _parent, _key_val, _reg, _key, _keyw, _gate, _mux, _muxw, _div0, _div0w)
/* For display clock */
#define DISPCLK_DEF(_id, _name, _parent_id, _parent_name, _reg, _divn, \
@@ -255,6 +265,7 @@ struct aic_clk_ops {
.pix_divsel_bit = _pix_divsel, \
.pix_divsel_mask = ((1 << _pix_divsel_width) - 1), \
.comm.ops = &aic_clk_disp_ops, \
.comm.name = _name, \
}
#define DISPCLK(_id, _name, _parent_id, _parent_name, _reg, _divn, _nwidth, \
_divm, _mwidth, _divl, _lwidth, _pix_divsel, \