v1.0.3

2025-12-14 18:38:55 +00:00 · 2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
--- a/bsp/artinchip/sys/d21x/include/aic_arch.h
+++ b/bsp/artinchip/sys/d21x/include/aic_arch.h
@@ -32,8 +32,6 @@

 #ifdef __riscv_xthead
 #ifdef __riscv_xtheade
-#define CONFIG_THEAD_EXT_SPUSHEN
-#define CONFIG_THEAD_EXT_SPSWAPEN
 #endif
 #endif

--- a/bsp/artinchip/sys/d21x/include/aic_dma_id.h
+++ b/bsp/artinchip/sys/d21x/include/aic_dma_id.h
@@ -28,4 +28,6 @@
 #define DMA_ID_UART6        22
 #define DMA_ID_UART7        23

+#define AIC_DMA_PORTS       24
+
 #endif
--- a/bsp/artinchip/sys/d21x/include/core_rv64.h
+++ b/bsp/artinchip/sys/d21x/include/core_rv64.h
@@ -970,17 +970,26 @@ __STATIC_INLINE void csi_dcache_invalid_range(phy_addr_t addr, u32 dsize)
    s32 op_size = dsize + addr % CACHE_LINE_SIZE;
    phy_addr_t op_addr = addr & CACHE_INV_ADDR_Msk;

+    if (op_size % CACHE_LINE_SIZE)
+        op_size += CACHE_LINE_SIZE - op_size % CACHE_LINE_SIZE;
    if ((op_size != dsize) || (op_addr != addr))
        printf("Alarm! Invalid cache out of range: 0x%x[%d] > 0x%x[%d]\n",
               op_addr, op_size, addr, dsize);

    __DSB();

+#ifdef __riscv_xthead
    while (op_size > 0) {
        __DCACHE_IPA(op_addr);
        op_addr += CACHE_LINE_SIZE;
        op_size -= CACHE_LINE_SIZE;
    }
+#else
+    register unsigned long c_addr asm("a5") = op_addr;
+    unsigned long end = op_addr + op_size;
+    for (; c_addr < end; c_addr += CACHE_LINE_SIZE)
+        asm volatile (".long 0x02a7800b"); /* dcache.ipa a5 */
+#endif

    __DSB();
    __ISB();
@@ -998,21 +1007,30 @@ __STATIC_INLINE void csi_dcache_invalid_range(phy_addr_t addr, u32 dsize)
 __STATIC_INLINE void csi_dcache_clean_range(phy_addr_t addr, u32 dsize)
 {

-#if (__DCACHE_PRESENT == 1)
+#if (__DCACHE_PRESENT == 1U)
    s32 op_size = dsize + addr % CACHE_LINE_SIZE;
    phy_addr_t op_addr = addr & CACHE_INV_ADDR_Msk;

+    if (op_size % CACHE_LINE_SIZE)
+        op_size += CACHE_LINE_SIZE - op_size % CACHE_LINE_SIZE;
    if ((op_size != dsize) || (op_addr != addr))
        printf("Alarm! Clean cache out of range: 0x%x[%d] > 0x%x[%d]\n",
               op_addr, op_size, addr, dsize);

    __DSB();

+#ifdef __riscv_xthead
    while (op_size > 0) {
        __DCACHE_CPA(op_addr);
        op_addr += CACHE_LINE_SIZE;
        op_size -= CACHE_LINE_SIZE;
    }
+#else
+    register unsigned long c_addr asm("a5") = op_addr;
+    unsigned long end = op_addr + op_size;
+    for (; c_addr < end; c_addr += CACHE_LINE_SIZE)
+        asm volatile (".long 0x0297800b"); /* dcache.cpa a5 */
+#endif

    __DSB();
    __ISB();
@@ -1034,17 +1052,26 @@ __STATIC_INLINE void csi_dcache_clean_invalid_range(phy_addr_t addr, u32 dsize)
    s32 op_size = dsize + addr % CACHE_LINE_SIZE;
    phy_addr_t op_addr = addr & CACHE_INV_ADDR_Msk;

+    if (op_size % CACHE_LINE_SIZE)
+        op_size += CACHE_LINE_SIZE - op_size % CACHE_LINE_SIZE;
    if ((op_size != dsize) || (op_addr != addr))
        printf("Alarm! Clean&Invalid cache out of range: 0x%x[%d] > 0x%x[%d]\n",
               op_addr, op_size, addr, dsize);

    __DSB();

+#ifdef __riscv_xthead
    while (op_size > 0) {
        __DCACHE_CIPA(op_addr);
        op_addr += CACHE_LINE_SIZE;
        op_size -= CACHE_LINE_SIZE;
    }
+#else
+    register unsigned long c_addr asm("a5") = op_addr;
+    unsigned long end = op_addr + op_size;
+    for (; c_addr < end; c_addr += CACHE_LINE_SIZE)
+        asm volatile (".long 0x02b7800b"); /* dcache.cipa a5 */
+#endif

    __DSB();
    __ISB();
@@ -1058,7 +1085,6 @@ __STATIC_INLINE void csi_dcache_clean_invalid_range(phy_addr_t addr, u32 dsize)
  */
 __STATIC_INLINE void csi_cache_set_range (uint64_t index, uint64_t baseAddr, uint64_t size, uint64_t enable)
 {
-    ;
 }

 /**
@@ -1067,7 +1093,6 @@ __STATIC_INLINE void csi_cache_set_range (uint64_t index, uint64_t baseAddr, uin
  */
 __STATIC_INLINE void csi_cache_enable_profile(void)
 {
-    ;
 }

 /**
@@ -1076,7 +1101,6 @@ __STATIC_INLINE void csi_cache_enable_profile(void)
  */
 __STATIC_INLINE void csi_cache_disable_profile(void)
 {
-    ;
 }

 /**
@@ -1085,7 +1109,6 @@ __STATIC_INLINE void csi_cache_disable_profile(void)
  */
 __STATIC_INLINE void csi_cache_reset_profile(void)
 {
-    ;
 }

 /**
--- a/bsp/artinchip/sys/d21x/include/cpuport.h
+++ b/bsp/artinchip/sys/d21x/include/cpuport.h
@@ -14,6 +14,9 @@
 #include <rtconfig.h>
 #include <aic_arch.h>

+#define TSPEND_ADDR             (CPU_BASE + 0x4000000)
+#define TSPEND_NEED_CLEAR
+
 /* bytes of register width  */
 #ifdef ARCH_RISCV64
 #define DFSTORE                 fsd
--- a/bsp/artinchip/sys/d21x/include/csi_rv64_gcc.h
+++ b/bsp/artinchip/sys/d21x/include/csi_rv64_gcc.h
@@ -1345,7 +1345,7 @@ __ALWAYS_STATIC_INLINE void __STOP(void)
 */
 __ALWAYS_STATIC_INLINE void __ISB(void)
 {
-    __ASM volatile("fence");
+    __ASM volatile("fence.i");
 }


@@ -1360,13 +1360,17 @@ __ALWAYS_STATIC_INLINE void __DSB(void)
 }

 /**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
+  \brief   Synchronization and clear instruction.
+  \details Ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions
+           retire later than this instruction, and clears the pipeline when this instruction retires.
 */
 __ALWAYS_STATIC_INLINE void __SYNC_IS(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("sync.is");
+#else
+    asm volatile (".long 0x01b0000b"); /* sync.is */
+#endif
 }

 /**
@@ -1375,7 +1379,11 @@ __ALWAYS_STATIC_INLINE void __SYNC_IS(void)
 */
 __ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("icache.iall");
+#else
+    asm volatile (".long 0x0100000b"); /* icache.iall */
+#endif
 }

 /**
@@ -1384,7 +1392,11 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
 */
 __ALWAYS_STATIC_INLINE void __ICACHE_IALLS(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("icache.ialls");
+#else
+    asm volatile (".long 0x0110000b"); /* icache.ialls */
+#endif
 }

 /**
@@ -1394,7 +1406,13 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IALLS(void)
 */
 __ALWAYS_STATIC_INLINE void __ICACHE_IPA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("icache.ipa %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x0385000b"); /* icache.ipa a0 */
+    i = i;
+#endif
 }

 /**
@@ -1404,7 +1422,13 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IPA(uint64_t addr)
 */
 __ALWAYS_STATIC_INLINE void __ICACHE_IVA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("icache.iva %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x0305000b"); /* icache.iva a0 */
+    i = i;
+#endif
 }

 /**
@@ -1413,7 +1437,11 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IVA(uint64_t addr)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.iall");
+#else
+    asm volatile (".long 0x0020000b"); /* dcache.iall */
+#endif
 }

 /**
@@ -1422,7 +1450,11 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.call");
+#else
+    asm volatile (".long 0x0010000b"); /* dcache.call */
+#endif
 }

 /**
@@ -1431,7 +1463,11 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.ciall");
+#else
+    asm volatile (".long 0x0030000b"); /* dcache.ciall */
+#endif
 }

 #if (__L2CACHE_PRESENT == 1U)
@@ -1441,7 +1477,11 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
 */
 __ALWAYS_STATIC_INLINE void __L2CACHE_IALL(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("l2cache.iall");
+#else
+    asm volatile (".long 0x0160000b"); /* l2cache.iall */
+#endif
 }

 /**
@@ -1450,7 +1490,11 @@ __ALWAYS_STATIC_INLINE void __L2CACHE_IALL(void)
 */
 __ALWAYS_STATIC_INLINE void __L2CACHE_CALL(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("l2cache.call");
+#else
+    asm volatile (".long 0x0150000b"); /* l2cache.call */
+#endif
 }

 /**
@@ -1459,7 +1503,11 @@ __ALWAYS_STATIC_INLINE void __L2CACHE_CALL(void)
 */
 __ALWAYS_STATIC_INLINE void __L2CACHE_CIALL(void)
 {
+#ifdef __riscv_xthead
    __ASM volatile("l2cache.ciall");
+#else
+    asm volatile (".long 0x0170000b"); /* l2cache.ciall */
+#endif
 }
 #endif

@@ -1471,7 +1519,13 @@ __ALWAYS_STATIC_INLINE void __L2CACHE_CIALL(void)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.ipa %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x02a5000b"); /* dcache.ipa a0 */
+    i = i;
+#endif
 }

 /**
@@ -1481,7 +1535,13 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IPA(uint64_t addr)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_IVA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.iva %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x0265000b"); /* dcache.iva a0 */
+    i = i;
+#endif
 }

 /**
@@ -1491,7 +1551,13 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IVA(uint64_t addr)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.cpa %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x0295000b"); /* dcache.cpa a0 */
+    i = i;
+#endif
 }

 /**
@@ -1501,7 +1567,13 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CPA(uint64_t addr)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_CVA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.cva %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x0255000b"); /* dcache.cva a0 */
+    i = i;
+#endif
 }

 /**
@@ -1511,7 +1583,13 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CVA(uint64_t addr)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.cipa %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x02b5000b"); /* dcache.cipa a0 */
+    i = i;
+#endif
 }

 /**
@@ -1521,7 +1599,13 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CIPA(uint64_t addr)
 */
 __ALWAYS_STATIC_INLINE void __DCACHE_CIVA(uint64_t addr)
 {
+#ifdef __riscv_xthead
    __ASM volatile("dcache.civa %0" : : "r"(addr));
+#else
+    register unsigned long i asm("a0") = addr;
+    asm volatile (".long 0x0275000b"); /* dcache.civa a0 */
+    i = i;
+#endif
 }