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刘可亮
2024-01-27 08:47:24 +08:00
parent d3bd993b5f
commit 9f7ba67007
2345 changed files with 74421 additions and 76616 deletions
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8
packages/third-party/cherryusb/port/ehci/README.md vendored
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@@ -18,6 +18,14 @@
- Nuvoton all series
### Artinchip
- d13x, d21x
### Intel
Intel 6 Series Chipset and Intel C200 Series Chipset
## Before Use
Your should implement `usb_hc_low_level_init`.

98
packages/third-party/cherryusb/port/ehci/usb_ehci_priv.h vendored
View File

@@ -5,17 +5,13 @@
#include "usbh_hub.h"
#include "usb_hc_ehci.h"
#ifndef USBH_IRQHandler
#define USBH_IRQHandler USBH_IRQHandler
#endif
#define EHCI_HCCR ((struct ehci_hccr *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET))
#define EHCI_HCOR ((struct ehci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCOR_OFFSET))
#define EHCI_HCCR ((struct ehci_hccr *)CONFIG_USB_EHCI_HCCR_BASE)
#define EHCI_HCOR ((struct ehci_hcor *)CONFIG_USB_EHCI_HCOR_BASE)
#define EHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x))
#define EHCI_ADDRALIGN32(x) ((uint32_t)(uintptr_t)(x) & ~0x1F)
#define EHCI_ADDR2QH(x) ((struct ehci_qh_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F))
#define EHCI_ADDR2ITD(x) ((struct ehci_itd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F))
#define EHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x) & ~0x1F)
#define EHCI_ADDR2QH(x) ((struct ehci_qh_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F))
#define EHCI_ADDR2QTD(x) ((struct ehci_qtd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F))
#define EHCI_ADDR2ITD(x) ((struct ehci_itd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F))
#if CONFIG_USB_EHCI_FRAME_LIST_SIZE == 1024
#define EHCI_PERIOIDIC_QH_NUM 11
@@ -28,83 +24,53 @@
#endif
#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM
#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USBHOST_PIPE_NUM * 3)
#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USBHOST_PIPE_NUM + 3)
#define CONFIG_USB_EHCI_ITD_NUM 20
#ifdef CONFIG_USB_DCACHE_ENABLE
#if (CACHE_LINE_SIZE >= 32)
#define EHCI_DESC_ALIGN CACHE_LINE_SIZE
#else
#define EHCI_DESC_ALIGN 32
#endif
#define EHCI_DESC_HW_ALIGN __attribute__((aligned(EHCI_DESC_ALIGN)))
#else
#define EHCI_DESC_ALIGN 32
#define EHCI_DESC_HW_ALIGN
#endif
extern uint8_t usbh_get_port_speed(const uint8_t port);
struct ehci_qh_hw;
struct ehci_itd_hw;
struct ehci_pipe {
uint8_t dev_addr;
uint8_t ep_addr;
uint8_t ep_type;
uint8_t ep_interval;
uint8_t speed;
uint8_t mult;
uint16_t ep_mps;
bool toggle;
bool inuse;
uint32_t xfrd;
bool waiter;
usb_osal_sem_t waitsem;
struct usbh_hubport *hport;
struct ehci_qh_hw *qh;
struct usbh_urb *urb;
uint8_t mf_unmask;
uint8_t mf_valid;
uint8_t iso_packet_idx;
uint8_t remain_itd_num;
};
extern uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port);
struct ehci_qh_hw {
struct ehci_qh hw;
uint32_t first_qtd EHCI_DESC_HW_ALIGN;
struct ehci_pipe *pipe;
} __attribute__((aligned(EHCI_DESC_ALIGN)));
USB_MEM_ALIGNX struct ehci_qh hw;
USB_MEM_ALIGNX uint32_t first_qtd;
struct usbh_urb *urb;
uint8_t remove_in_iaad;
usb_osal_sem_t waitsem;
} __attribute__((aligned(32)));
struct ehci_qtd_hw {
struct ehci_qtd hw;
USB_MEM_ALIGNX struct ehci_qtd hw;
USB_MEM_ALIGNX struct usbh_urb *urb;
uint32_t total_len;
#ifdef CONFIG_USB_DCACHE_ENABLE
void * buffer EHCI_DESC_HW_ALIGN;
void * buffer;
void * align_buffer;
uint32_t buffer_len;
uint32_t align_buffer_len;
char dir_in; /* 0=out, 1=in */
#endif
} __attribute__((aligned(EHCI_DESC_ALIGN)));
} __attribute__((aligned(32)));
struct ehci_itd_hw {
struct ehci_itd hw;
struct usbh_urb *urb EHCI_DESC_HW_ALIGN;
struct ehci_pipe *pipe;
USB_MEM_ALIGNX struct ehci_itd hw;
USB_MEM_ALIGNX struct usbh_urb *urb;
uint16_t start_frame;
uint8_t mf_unmask;
uint8_t mf_valid;
uint32_t pkt_idx[8];
usb_slist_t list;
} __attribute__((aligned(EHCI_DESC_ALIGN)));
} __attribute__((aligned(32)));
struct ehci_hcd {
bool ehci_qh_used[CONFIG_USB_EHCI_QH_NUM];
bool ehci_qtd_used[CONFIG_USB_EHCI_QTD_NUM];
bool ehci_itd_used[CONFIG_USB_EHCI_ITD_NUM];
struct ehci_pipe pipe_pool[CONFIG_USB_EHCI_QH_NUM];
};
extern struct ehci_hcd g_ehci_hcd;
extern uint32_t g_framelist[];
extern struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS];
extern uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_FRAME_LIST_SIZE];
int ehci_iso_pipe_init(struct ehci_pipe *pipe, struct usbh_urb *urb);
void ehci_remove_itd_urb(struct usbh_urb *urb);
void ehci_scan_isochronous_list(void);
int ehci_iso_urb_init(struct usbh_bus *bus, struct usbh_urb *urb);
void ehci_remove_itd_urb(struct usbh_bus *bus, struct usbh_urb *urb);
void ehci_scan_isochronous_list(struct usbh_bus *bus);
#endif
#endif

101
packages/third-party/cherryusb/port/ehci/usb_glue_aic.c vendored
View File

@@ -12,55 +12,98 @@
extern void USBH_IRQHandler(void);
void usb_hc_low_level_init(void)
typedef struct aic_ehci_config {
uint32_t base_addr;
uint32_t clk_id;
uint32_t rst_id;
uint32_t phy_clk_id;
uint32_t phy_rst_id;
uint32_t irq_num;
}aic_ehci_config_t;
aic_ehci_config_t config[] = {
#ifdef AIC_USING_USB0_HOST
{
USB_HOST0_BASE,
CLK_USBH0,
RESET_USBH0,
CLK_USB_PHY0,
RESET_USBPHY0,
USB_HOST0_EHCI_IRQn
},
#else
{
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF
},
#endif
#ifdef AIC_USING_USB1_HOST
{
USB_HOST1_BASE,
CLK_USBH1,
RESET_USBH1,
CLK_USB_PHY1,
RESET_USBPHY1,
USB_HOST1_EHCI_IRQn
}
#endif
};
void usb_hc_low_level_init(struct usbh_bus *bus)
{
uint32_t val;
int i = 0;
for (i=0; i<sizeof(config)/sizeof(aic_ehci_config_t); i++) {
if (bus->hcd.reg_base == config[i].base_addr)
break;
}
if (i == sizeof(config)/sizeof(aic_ehci_config_t))
return;
/* set usb0 phy switch: Host/Device */
#ifdef AIC_USING_USB0_HOST
syscfg_usb_phy0_sw_host(1);
#endif
if (i == 0)
syscfg_usb_phy0_sw_host(1);
/* enable clock */
hal_clk_enable(config[i].phy_clk_id);
hal_clk_enable(config[i].clk_id);
aicos_udelay(300);
hal_reset_assert(config[i].phy_rst_id);
hal_reset_assert(config[i].rst_id);
aicos_udelay(300);
hal_reset_deassert(config[i].phy_rst_id);
hal_reset_deassert(config[i].rst_id);
aicos_udelay(300);
/* set phy type: UTMI/ULPI */
val = readl((volatile void *)(unsigned long)(CONFIG_USB_EHCI_HCCR_BASE+0x800));
val = readl((volatile void *)(unsigned long)(config[i].base_addr+0x800));
#ifdef FPGA_BOARD_ARTINCHIP
/* fpga phy type = ULPI */
writel((val & ~0x1U), (volatile void *)(unsigned long)(CONFIG_USB_EHCI_HCCR_BASE+0x800));
writel((val & ~0x1U), (volatile void *)(unsigned long)(config[i].base_addr+0x800));
#else
/* board phy type = UTMI */
writel((val | 0x1), (volatile void *)(unsigned long)(CONFIG_USB_EHCI_HCCR_BASE+0x800));
writel((val | 0x1), (volatile void *)(unsigned long)(config[i].base_addr+0x800));
#endif
#if 0
/* Set AHB2STBUS_INSREG01
Set EHCI packet buffer IN/OUT threshold (in DWORDs)
Must increase the OUT threshold to avoid underrun. (FIFO size - 4)
*/
#ifdef FPGA_BOARD_ARTINCHIP
writel((32 | (127 << 16)), (volatile void *)(unsigned long)(CONFIG_USB_EHCI_HCCR_BASE+0x94));
#else
writel((32 | (32 << 16)), (volatile void *)(unsigned long)(CONFIG_USB_EHCI_HCCR_BASE+0x94));
#endif
#endif
/* enable clock */
hal_clk_enable(CONFIG_USB_EHCI_PHY_CLK);
hal_clk_enable(CONFIG_USB_EHCI_CLK);
aicos_udelay(300);
hal_reset_assert(CONFIG_USB_EHCI_PHY_RESET);
hal_reset_assert(CONFIG_USB_EHCI_RESET);
aicos_udelay(300);
hal_reset_deassert(CONFIG_USB_EHCI_PHY_RESET);
hal_reset_deassert(CONFIG_USB_EHCI_RESET);
aicos_udelay(300);
writel((32 | (127 << 16)), (volatile void *)(unsigned long)(config[i].base_addr+0x94));
/* register interrupt callback */
aicos_request_irq(CONFIG_USB_EHCI_IRQ_NUM, (irq_handler_t)USBH_IRQHandler,
0, "usb_host_ehci", NULL);
aicos_irq_enable(CONFIG_USB_EHCI_IRQ_NUM);
aicos_request_irq(config[i].irq_num, (irq_handler_t)USBH_IRQHandler,
0, "usb_host_ehci", bus);
aicos_irq_enable(config[i].irq_num);
}
uint8_t usbh_get_port_speed(const uint8_t port)
uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)
{
/* Defined by individual manufacturers */
uint32_t regval;

134
packages/third-party/cherryusb/port/ehci/usb_glue_bouffalo.c vendored Normal file
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@@ -0,0 +1,134 @@
#include "bflb_core.h"
#include "usbh_core.h"
#include "hardware/usb_v2_reg.h"
#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
#error "usb host must enable CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE"
#endif
#define BLFB_USB_BASE ((uint32_t)0x20072000)
#define BFLB_PDS_BASE ((uint32_t)0x2000e000)
#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */
#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */
/* 0x500 : usb_ctl */
#define PDS_REG_USB_SW_RST_N (1 << 0U)
#define PDS_REG_USB_EXT_SUSP_N (1 << 1U)
#define PDS_REG_USB_WAKEUP (1 << 2U)
#define PDS_REG_USB_L1_WAKEUP (1 << 3U)
#define PDS_REG_USB_DRVBUS_POL (1 << 4U)
#define PDS_REG_USB_IDDIG (1 << 5U)
/* 0x504 : usb_phy_ctrl */
#define PDS_REG_USB_PHY_PONRST (1 << 0U)
#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U)
#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U)
#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT)
#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U)
#define PDS_REG_USB_PHY_PLLALIV (1 << 5U)
#define PDS_REG_PU_USB20_PSW (1 << 6U)
#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C)
#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710)
extern void USBH_IRQHandler(struct usbh_bus *bus);
static void bflb_usb_phy_init(void)
{
uint32_t regval;
/* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */
/* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
/* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */
/* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */
/* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */
/* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */
/* #1.2ms; wait UCLK */
/* wait(soc616_b0.usb_uclk); */
regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval |= PDS_REG_PU_USB20_PSW;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
regval |= PDS_REG_USB_PHY_PONRST;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
/* greater than 5T */
bflb_mtimer_delay_us(1);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval &= ~PDS_REG_USB_SW_RST_N;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
/* greater than 5T */
bflb_mtimer_delay_us(1);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval |= PDS_REG_USB_EXT_SUSP_N;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
/* wait UCLK 1.2ms */
bflb_mtimer_delay_ms(3);
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval |= PDS_REG_USB_SW_RST_N;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
bflb_mtimer_delay_ms(2);
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
uint32_t regval;
bflb_usb_phy_init();
bflb_irq_attach(37, USBH_IRQHandler, NULL);
bflb_irq_enable(37);
/* enable device-A for host */
regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval &= ~PDS_REG_USB_IDDIG;
putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
regval |= USB_A_BUS_DROP_HOV;
regval &= ~USB_A_BUS_REQ_HOV;
putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
bflb_mtimer_delay_ms(10);
/* enable vbus and bus control */
regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
regval &= ~USB_A_BUS_DROP_HOV;
regval |= USB_A_BUS_REQ_HOV;
putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET);
regval |= USB_MDEV_INT;
regval |= USB_MOTG_INT;
regval &= ~USB_MHC_INT;
putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET);
}
uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)
{
uint8_t speed = 3;
speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
if (speed == 0) {
return USB_SPEED_FULL;
} else if (speed == 1) {
return USB_SPEED_LOW;
} else if (speed == 2) {
return USB_SPEED_HIGH;
}
return USB_SPEED_HIGH;
}

77
packages/third-party/cherryusb/port/ehci/usb_glue_hpm.c vendored
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@@ -3,39 +3,30 @@
#include "hpm_soc.h"
#include "hpm_usb_drv.h"
#define USB_PHY_INIT_DELAY_COUNT (16U) /**< a delay count for USB phy initialization */
#if !defined(CONFIG_USB_EHCI_HPMICRO) || !CONFIG_USB_EHCI_HPMICRO
#error "hpm ehci must set CONFIG_USB_EHCI_HPMICRO=1"
#endif
/* Initialize USB phy */
static void usb_phy_init(USB_Type *ptr)
{
uint32_t status;
#if !defined(CONFIG_USB_EHCI_HCOR_OFFSET) || CONFIG_USB_EHCI_HCOR_OFFSET != 0x140
#error "hpm ehci must config CONFIG_USB_EHCI_HCOR_OFFSET to 0x140"
#endif
ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* set otg_utmi_reset_sw for naneng usbphy */
ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* clr otg_utmi_suspend_m for naneng usbphy */
ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clr cfg_rst_n */
#if defined(CONFIG_USB_EHCI_PRINT_HW_PARAM) || !defined(CONFIG_USB_EHCI_PORT_POWER)
#error "hpm ehci must enable CONFIG_USB_EHCI_PORT_POWER and disable CONFIG_USB_EHCI_PRINT_HW_PARAM"
#endif
do {
status = USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(ptr->OTG_CTRL0); /* wait for reset status */
} while (status == 0);
struct usbh_bus *hpm_usb_bus0;
ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */
#ifdef HPM_USB1_BASE
struct usbh_bus *hpm_usb_bus1;
#endif
for (int i = 0; i < USB_PHY_INIT_DELAY_COUNT; i++) {
ptr->PHY_CTRL0 = USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(0); /* used for delay */
}
ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */
/* otg utmi clock detection */
ptr->PHY_STATUS |= USB_PHY_STATUS_UTMI_CLK_VALID_MASK; /* write 1 to clear valid status */
do {
status = USB_PHY_STATUS_UTMI_CLK_VALID_GET(ptr->PHY_STATUS); /* get utmi clock status */
} while (status == 0);
ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* set cfg_rst_n */
ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* set otg_suspendm */
}
const uint8_t hpm_irq_table[] = {
IRQn_USB0,
#ifdef HPM_USB1_BASE
IRQn_USB1
#endif
};
static void usb_host_mode_init(USB_Type *ptr)
{
@@ -56,22 +47,23 @@ static void usb_host_mode_init(USB_Type *ptr)
ptr->USBCMD &= ~USB_USBCMD_ITC_MASK;
}
void usb_hc_low_level_init()
void usb_hc_low_level_init(struct usbh_bus *bus)
{
usb_phy_init((USB_Type *)HPM_USB0_BASE);
intc_m_enable_irq(IRQn_USB0);
usb_phy_init((USB_Type *)(bus->hcd.reg_base));
intc_m_enable_irq(hpm_irq_table[bus->hcd.hcd_id]);
}
void usb_hc_low_level2_init()
void usb_hc_low_level2_init(struct usbh_bus *bus)
{
usb_host_mode_init((USB_Type *)HPM_USB0_BASE);
usb_host_mode_init((USB_Type *)(bus->hcd.reg_base));
}
uint8_t usbh_get_port_speed(const uint8_t port)
uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)
{
(void)port;
uint8_t speed;
speed = usb_get_port_speed((USB_Type *)HPM_USB0_BASE);
speed = usb_get_port_speed((USB_Type *)(bus->hcd.reg_base));
if (speed == 0x00) {
return USB_SPEED_FULL;
@@ -86,17 +78,18 @@ uint8_t usbh_get_port_speed(const uint8_t port)
return 0;
}
extern void USBH_IRQHandler(void);
extern void USBH_IRQHandler(struct usbh_bus *bus);
void isr_usb0(void)
void isr_usbh0(void)
{
USBH_IRQHandler();
USBH_IRQHandler(hpm_usb_bus0);
}
SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usb0)
SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usbh0)
#ifdef HPM_USB1_BASE
void isr_usb1(void)
void isr_usbh1(void)
{
USBH_IRQHandler(hpm_usb_bus1);
}
SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usb1)
#endif
SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usbh1)
#endif

55
packages/third-party/cherryusb/port/ehci/usb_glue_intel.c vendored Normal file
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@@ -0,0 +1,55 @@
#ifdef __rtems__
#include <rtems.h>
#include <rtems/pci.h>
#include <bsp/irq.h>
#include "usbh_core.h"
uint32_t echi_base;
static int ehci_bus;
static int ehci_slot;
static int ehci_function;
static int ehci_vector;
extern void USBH_IRQHandler(struct usbh_bus *bus);
void ehci_pci_scan(int bus, int slot, int fun, int vector)
{
ehci_bus = bus;
ehci_slot = slot;
ehci_function = fun;
ehci_vector = vector;
pci_read_config_dword(bus, slot, fun, PCI_BASE_ADDRESS_0, &echi_base);
}
void usb_hc_low_level_init(struct usbh_bus *bus)
{
//set software own ehci
uint32_t legacy_val;
pci_write_config_dword(ehci_bus, ehci_slot, ehci_function, 0x68, 1 << 24);
pci_read_config_dword(ehci_bus, ehci_slot, ehci_function, 0x68, &legacy_val);
if ((legacy_val & 0x01010000) == 0x01000000)
printf("OS owned echi\n");
else
printf("BIOS owned echi\n");
rtems_status_code sc;
sc = rtems_interrupt_handler_install(
ehci_vector,
"USBirq",
RTEMS_INTERRUPT_SHARED,
USBH_IRQHandler,
(void *)bus);
if (sc != RTEMS_SUCCESSFUL) {
printf("USB install isr falied,%s\n", rtems_status_text(sc));
return;
}
}
uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)
{
printf("USB_SPEED_HIGH present\n");
return USB_SPEED_HIGH;
}
#endif

1248
packages/third-party/cherryusb/port/ehci/usb_hc_ehci.c vendored
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File diff suppressed because it is too large Load Diff

4
packages/third-party/cherryusb/port/ehci/usb_hc_ehci.h vendored
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@@ -1,7 +1,7 @@
/*
* Copyright 2020 The Apache Software Foundation
* Copyright 2022 sakumisu
*
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef USB_HC_EHCI_H
@@ -302,7 +302,7 @@ struct ehci_hcor {
uint32_t ctrldssegment; /* 0x10: 4G Segment Selector */
uint32_t periodiclistbase; /* 0x14: Frame List Base Address */
uint32_t asynclistaddr; /* 0x18: Next Asynchronous List Address */
#ifndef CONFIG_USB_ECHI_HCOR_RESERVED_DISABLE
#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
uint32_t reserved[9];
#endif
uint32_t configflag; /* 0x40: Configured Flag Register */