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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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336 lines
13 KiB
C
336 lines
13 KiB
C
/*
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* Copyright (c) 2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: jiji.chen <jiji.chen@artinchip.com>
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*/
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#ifndef _AIC_HAL_SYSCFG_REGS_H_
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#define _AIC_HAL_SYSCFG_REGS_H_
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#include <aic_common.h>
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#include <aic_soc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* The register definition of SYSCFG V10 */
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#define LDO30_CFG (SYSCFG_BASE + 0x020)
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#define LDO25_CFG (SYSCFG_BASE + 0x024)
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#define LDO1x_CFG (SYSCFG_BASE + 0x028)
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#define DDR_VREF (SYSCFG_BASE + 0x040)
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#define DDR_REXT (SYSCFG_BASE + 0x044)
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#define USB0_REXT (SYSCFG_BASE + 0x048)
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#define USB1_REXT (SYSCFG_BASE + 0x04C)
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#define EPHY_REXT (SYSCFG_BASE + 0x050)
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#define PSEN_CFG (SYSCFG_BASE + 0x0C0)
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#define PSEN_CNT_VAL (SYSCFG_BASE + 0x0C4)
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#define SYS_SRAM_PAR (SYSCFG_BASE + 0x100)
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#define CPU_SRAM_PAR (SYSCFG_BASE + 0x104)
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#define DDR_SRAM_PAR (SYSCFG_BASE + 0x108)
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#define VE_SRAM_PAR (SYSCFG_BASE + 0x10C)
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#define GE_SRAM_PAR (SYSCFG_BASE + 0x110)
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#define SRAM_CLK_CFG (SYSCFG_BASE + 0x140)
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#define USB0_CFG (SYSCFG_BASE + 0x40C)
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#define GMAC0_CFG (SYSCFG_BASE + 0x410)
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#define GMAC1_CFG (SYSCFG_BASE + 0x414)
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#define EPHY_CFG0 (SYSCFG_BASE + 0x418)
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#define EPHY_CFG1 (SYSCFG_BASE + 0x41C)
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#define DBG_CFG (SYSCFG_BASE + 0xF00)
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#define SYSCFG_VER (SYSCFG_BASE + 0xFFC)
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/* The field definition of LDO30_CFG */
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#define LDO30_CFG_ATB_ANA_EN BIT(27)
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#define LDO30_CFG_ATB_ANA_SEL_MASK GENMASK(26, 24)
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#define LDO30_CFG_ATB_ANA_SEL_SHIFT (24)
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#define LDO30_CFG_ATB_BIAS_EN BIT(22)
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#define LDO30_CFG_ATB_BIAS_SEL_MASK GENMASK(21, 20)
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#define LDO30_CFG_ATB_BIAS_SEL_SHIFT (20)
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#define LDO30_CFG_LVDS0_IBIAS_EN BIT(18)
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#define LDO30_CFG_LVDS1_IBIAS_EN BIT(17)
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#define LDO30_CFG_BAK_IBIAS_EN BIT(16)
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#define LDO30_CFG_BG_CTRL_MASK GENMASK(15, 8)
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#define LDO30_CFG_BG_CTRL_SHIFT (8)
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#define LDO30_CFG_RTC_VAL_SEL_MASK GENMASK(6, 4)
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#define LDO30_CFG_RTC_VAL_SEL_SHIFT (4)
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#define LDO30_CFG_LDO_AVCC_EN BIT(3)
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#define LDO30_CFG_LDO_VAL_MASK GENMASK(2, 0)
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#define LDO30_CFG_LDO_VAL_SHIFT (0)
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/* The field definition of LDO25_CFG */
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#define LDO25_CFG_ATB_ANA_EN BIT(27)
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#define LDO25_CFG_ATB_ANA_SEL_MASK GENMASK(26, 24)
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#define LDO25_CFG_ATB_ANA_SEL_SHIFT (24)
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#define LDO25_CFG_ATB_BIAS_EN BIT(22)
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#define LDO25_CFG_ATB_BIAS_SEL_MASK GENMASK(21, 20)
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#define LDO25_CFG_ATB_BIAS_SEL_SHIFT (20)
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#define LDO25_CFG_BG_CTRL_MASK GENMASK(15, 8)
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#define LDO25_CFG_BG_CTRL_SHIFT (8)
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#define LDO25_CFG_LDO25_EN BIT(3)
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#define LDO25_CFG_LDO25_VAL_MASK GENMASK(2, 0)
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#define LDO25_CFG_LDO25_VAL_SHIFT (0)
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/* The field definition of LDO1x_CFG */
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#define LDO1x_CFG_LDO1X_VAL_FB_MASK GENMASK(6, 4)
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#define LDO1x_CFG_LDO1X_VAL_FB_SHIFT (4)
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#define LDO1x_CFG_LDO1X_EN BIT(3)
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#define LDO1x_CFG_LDO1X_VAL_MASK GENMASK(2, 0)
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#define LDO1x_CFG_LDO1X_VAL_SHIFT (0)
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/* The field definition of DDR_VREF */
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#define DDR_VREF_RES1_SEL_MASK GENMASK(11, 8)
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#define DDR_VREF_RES1_SEL_SHIFT (8)
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#define DDR_VREF_RES0_SEL_MASK GENMASK(3, 0)
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#define DDR_VREF_RES0_SEL_SHIFT (0)
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/* The field definition of DDR_REXT */
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#define DDR_REXT_RES_CAL_EN BIT(8)
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#define DDR_REXT_RES_CAL_VAL_MASK GENMASK(7, 0)
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#define DDR_REXT_RES_CAL_VAL_SHIFT (0)
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/* The field definition of USB0_REXT */
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#define USB0_REXT_RES_CAL_EN BIT(8)
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#define USB0_REXT_RES_CAL_VAL_MASK GENMASK(7, 0)
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#define USB0_REXT_RES_CAL_VAL_SHIFT (0)
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#define USB0_REXT_RES_EN_VAL(v) (((v) << USB0_REXT_RES_CAL_VAL_SHIFT) & USB0_REXT_RES_CAL_VAL_MASK)
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/* The field definition of USB1_REXT */
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#define USB1_REXT_RES_CAL_EN BIT(8)
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#define USB1_REXT_RES_CAL_VAL_MASK GENMASK(7, 0)
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#define USB1_REXT_RES_CAL_VAL_SHIFT (0)
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#define USB1_REXT_RES_EN_VAL(v) (((v) << USB1_REXT_RES_CAL_VAL_SHIFT) & USB1_REXT_RES_CAL_VAL_MASK)
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/* The field definition of EPHY_REXT */
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#define EPHY_REXT_RES_CAL_EN BIT(8)
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#define EPHY_REXT_RES_CAL_VAL_MASK GENMASK(7, 0)
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#define EPHY_REXT_RES_CAL_VAL_SHIFT (0)
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/* The field definition of PSEN_CFG */
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#define PSEN_CFG_CNT_TIME_MASK GENMASK(31, 16)
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#define PSEN_CFG_CNT_TIME_SHIFT (16)
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#define PSEN_CFG_RO_SEL_MASK GENMASK(3, 1)
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#define PSEN_CFG_RO_SEL_SHIFT (1)
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#define PSEN_CFG_PSEN_START BIT(0)
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/* The field definition of PSEN_CNT_VAL */
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#define PSEN_CNT_VAL_CNT_VAL_MASK GENMASK(15, 0)
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#define PSEN_CNT_VAL_CNT_VAL_SHIFT (0)
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/* The field definition of SYS_SRAM_PAR */
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#define SYS_SRAM_PAR_SRAM_PAR_MASK GENMASK(31, 0)
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#define SYS_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of CPU_SRAM_PAR */
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#define CPU_SRAM_PAR_SRAM_PAR_MASK GENMASK(31, 0)
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#define CPU_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of DDR_SRAM_PAR */
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#define DDR_SRAM_PAR_SRAM_PAR_MASK GENMASK(31, 0)
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#define DDR_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of VE_SRAM_PAR */
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#define VE_SRAM_PAR_SRAM_PAR_MASK GENMASK(31, 0)
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#define VE_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of GE_SRAM_PAR */
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#define GE_SRAM_PAR_SRAM_PAR_MASK GENMASK(31, 0)
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#define GE_SRAM_PAR_SRAM_PAR_SHIFT (0)
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/* The field definition of SRAM_CLK_CFG */
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#define SRAM_CLK_CFG_SRAM_CLK_UNGATE_MASK GENMASK(15, 0)
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#define SRAM_CLK_CFG_SRAM_CLK_UNGATE_SHIFT (0)
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/* The field definition of USB0_CFG */
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#define USB0_CFG_DRD_MODE BIT(0)
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/* The field definition of GMAC0_CFG */
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#define GMAC0_CFG_GMAC_REFCLK_INV BIT(29)
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#define GMAC0_CFG_GMAC_REFDLY_SEL_MASK GENMASK(28, 24)
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#define GMAC0_CFG_GMAC_REFDLY_SEL_SHIFT (24)
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#define GMAC0_CFG_GMAC_RXCLK_INV BIT(23)
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#define GMAC0_CFG_GMAC_RXDLY_SEL_MASK GENMASK(22, 18)
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#define GMAC0_CFG_GMAC_RXDLY_SEL_SHIFT (18)
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#define GMAC0_CFG_GMAC_RXDLY_EN_VAL(v) (((v) << GMAC0_CFG_GMAC_RXDLY_SEL_SHIFT) & GMAC0_CFG_GMAC_RXDLY_SEL_MASK)
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#define GMAC0_CFG_GMAC_TXCLK_INV BIT(17)
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#define GMAC0_CFG_GMAC_TXDLY_SEL_MASK GENMASK(16, 12)
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#define GMAC0_CFG_GMAC_TXDLY_SEL_SHIFT (12)
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#define GMAC0_CFG_GMAC_TXDLY_EN_VAL(v) (((v) << GMAC0_CFG_GMAC_TXDLY_SEL_SHIFT) & GMAC0_CFG_GMAC_TXDLY_SEL_MASK)
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#define GMAC0_CFG_SW_TXCLK_DIV2_MASK GENMASK(11, 8)
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#define GMAC0_CFG_SW_TXCLK_DIV2_SHIFT (8)
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#define GMAC0_CFG_SW_TXCLK_DIV1_MASK GENMASK(7, 4)
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#define GMAC0_CFG_SW_TXCLK_DIV1_SHIFT (4)
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#define GMAC0_CFG_SW_TXCLK_DIV_EN BIT(2)
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#define GMAC0_CFG_RMII_EXTCLK_SEL BIT(1)
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#define GMAC0_CFG_PHY_RGMII_SEL BIT(0)
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/* The field definition of GMAC1_CFG */
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#define GMAC1_CFG_GMAC_REFCLK_INV BIT(29)
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#define GMAC1_CFG_GMAC_REFDLY_SEL_MASK GENMASK(28, 24)
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#define GMAC1_CFG_GMAC_REFDLY_SEL_SHIFT (24)
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#define GMAC1_CFG_GMAC_RXCLK_INV BIT(23)
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#define GMAC1_CFG_GMAC_RXDLY_SEL_MASK GENMASK(22, 18)
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#define GMAC1_CFG_GMAC_RXDLY_SEL_SHIFT (18)
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#define GMAC1_CFG_GMAC_RXDLY_EN_VAL(v) (((v) << GMAC1_CFG_GMAC_RXDLY_SEL_SHIFT) & GMAC1_CFG_GMAC_RXDLY_SEL_MASK)
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#define GMAC1_CFG_GMAC_TXCLK_INV BIT(17)
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#define GMAC1_CFG_GMAC_TXDLY_SEL_MASK GENMASK(16, 12)
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#define GMAC1_CFG_GMAC_TXDLY_SEL_SHIFT (12)
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#define GMAC1_CFG_GMAC_TXDLY_EN_VAL(v) (((v) << GMAC1_CFG_GMAC_TXDLY_SEL_SHIFT) & GMAC1_CFG_GMAC_TXDLY_SEL_MASK)
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#define GMAC1_CFG_SW_TXCLK_DIV2_MASK GENMASK(11, 8)
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#define GMAC1_CFG_SW_TXCLK_DIV2_SHIFT (8)
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#define GMAC1_CFG_SW_TXCLK_DIV1_MASK GENMASK(7, 4)
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#define GMAC1_CFG_SW_TXCLK_DIV1_SHIFT (4)
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#define GMAC1_CFG_SW_TXCLK_DIV_EN BIT(2)
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#define GMAC1_CFG_RMII_EXTCLK_SEL BIT(1)
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#define GMAC1_CFG_PHY_RGMII_SEL BIT(0)
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/* The field definition of EPHY_CFG0 */
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#define EPHY_CFG0_LED1_CYCLE_HIGH_MASK GENMASK(31, 28)
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#define EPHY_CFG0_LED1_CYCLE_HIGH_SHIFT (28)
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#define EPHY_CFG0_LED0_CYCLE_HIGH_MASK GENMASK(27, 24)
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#define EPHY_CFG0_LED0_CYCLE_HIGH_SHIFT (24)
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#define EPHY_CFG0_LED1_MODE BIT(9)
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#define EPHY_CFG0_LED0_MODE BIT(8)
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#define EPHY_CFG0_LED1_SEL_MASK GENMASK(6, 4)
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#define EPHY_CFG0_LED1_SEL_SHIFT (4)
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#define EPHY_CFG0_LED0_SEL_MASK GENMASK(2, 0)
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#define EPHY_CFG0_LED0_SEL_SHIFT (0)
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/* The field definition of EPHY_CFG1 */
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#define EPHY_CFG1_LED1_CYCLE_LOW_MASK GENMASK(31, 16)
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#define EPHY_CFG1_LED1_CYCLE_LOW_SHIFT (16)
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#define EPHY_CFG1_LED0_CYCLE_LOW_MASK GENMASK(15, 0)
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#define EPHY_CFG1_LED0_CYCLE_LOW_SHIFT (0)
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/* The field definition of DBG_CFG */
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#define DBG_CFG_DBG_KEY_MASK GENMASK(31, 16)
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#define DBG_CFG_DBG_KEY_SHIFT (16)
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#define DBG_CFG_DBG_MODE_SEL_MASK GENMASK(15, 14)
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#define DBG_CFG_DBG_MODE_SEL_SHIFT (14)
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#define DBG_CFG_DBG_CLK_SEL_MASK GENMASK(13, 8)
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#define DBG_CFG_DBG_CLK_SEL_SHIFT (8)
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#define DBG_CFG_DBG_OUT_SEL_MASK GENMASK(7, 0)
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#define DBG_CFG_DBG_OUT_SEL_SHIFT (0)
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/* The field definition of SYSCFG_VER */
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#define SYSCFG_VER_VERSION_MASK GENMASK(31, 0)
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#define SYSCFG_VER_VERSION_SHIFT (0)
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#define REFERENCE_VOLTAGE 28000
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#define VOLTAGE_SPACING 500
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static inline u32 syscfg_hw_read_ldo_cfg(void)
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{
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u32 ldo30_val;
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ldo30_val = readl(LDO30_CFG);
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ldo30_val &= LDO30_CFG_LDO_VAL_MASK;
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return ldo30_val * VOLTAGE_SPACING + REFERENCE_VOLTAGE;
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}
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static inline void syscfg_hw_usb_init(u32 res_val)
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{
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s32 __attribute__((unused)) val;
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#if defined(AIC_USING_USB0_HOST) || defined(AIC_USING_USB0_OTG) || defined(AICUPG_UDISK_ENABLE)
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val = readl(USB0_REXT);
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val &= ~USB0_REXT_RES_CAL_VAL_MASK;
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val |= USB0_REXT_RES_EN_VAL(res_val);
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val |= USB0_REXT_RES_CAL_EN;
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writel(val, USB0_REXT);
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#endif
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#if defined(AIC_USING_USB1_HOST) || defined(AIC_USING_USB1_OTG) || defined(AICUPG_UDISK_ENABLE)
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val = readl(USB1_REXT);
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val &= ~USB1_REXT_RES_CAL_VAL_MASK;
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val |= USB1_REXT_RES_EN_VAL(res_val);
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val |= USB1_REXT_RES_CAL_EN;
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writel(val, USB1_REXT);
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#endif
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}
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static inline void syscfg_hw_usb_phy0_set_host(void)
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{
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u32 val;
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val = readl(USB0_CFG);
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val &= ~USB0_CFG_DRD_MODE;
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writel(val, USB0_CFG);
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}
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static inline void syscfg_hw_usb_phy0_set_device(void)
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{
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u32 val;
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val = readl(USB0_CFG);
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val |= USB0_CFG_DRD_MODE;
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writel(val, USB0_CFG);
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}
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static inline void syscfg_hw_gmac0_init(void)
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{
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u32 val;
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val = readl(GMAC0_CFG);
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#ifdef AIC_DEV_GMAC0_RGMII
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val |= GMAC0_CFG_PHY_RGMII_SEL;
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#else
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val &= ~GMAC0_CFG_PHY_RGMII_SEL;
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#endif
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#ifdef AIC_DEV_GMAC0_PHY_EXTCLK
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val |= GMAC0_CFG_RMII_EXTCLK_SEL;
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#endif
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#if AIC_DEV_GMAC0_TXDELAY
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val |= GMAC0_CFG_GMAC_TXDLY_EN_VAL(AIC_DEV_GMAC0_TXDELAY);
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#endif
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#if AIC_DEV_GMAC0_RXDELAY
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val |= GMAC0_CFG_GMAC_RXDLY_EN_VAL(AIC_DEV_GMAC0_RXDELAY);
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#endif
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writel(val, GMAC0_CFG);
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}
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static inline void syscfg_hw_gmac1_init(void)
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{
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u32 val;
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val = readl(GMAC1_CFG);
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#ifdef AIC_DEV_GMAC1_RGMII
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val |= GMAC1_CFG_PHY_RGMII_SEL;
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#else
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val &= ~GMAC1_CFG_PHY_RGMII_SEL;
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#endif
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#ifdef AIC_DEV_GMAC1_PHY_EXTCLK
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val |= GMAC1_CFG_RMII_EXTCLK_SEL;
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#endif
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#if AIC_DEV_GMAC1_TXDELAY
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val |= GMAC1_CFG_GMAC_TXDLY_EN_VAL(AIC_DEV_GMAC1_TXDELAY);
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#endif
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#if AIC_DEV_GMAC1_RXDELAY
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val |= GMAC1_CFG_GMAC_RXDLY_EN_VAL(AIC_DEV_GMAC1_RXDELAY);
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#endif
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writel(val, GMAC1_CFG);
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}
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static inline void syscfg_hw_gmac_init(u32 gmac)
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{
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if (gmac == 0) {
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syscfg_hw_gmac0_init();
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} else if (gmac == 1) {
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syscfg_hw_gmac1_init();
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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