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43 lines
1.0 KiB
C
43 lines
1.0 KiB
C
/*
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* Copyright (c) 2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Xuan.Wen <xuan.wen@artinchip.com>
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*/
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#ifndef _AIC_QSPI_SLAVE_
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#define _AIC_QSPI_SLAVE_
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/* Write flow:
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* 1BYTE 3BYTE 512
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* 1. WRITE ADDRESS DATA
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*
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* Read flow:
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* 1. LOAD ADDRESS
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* 2. GET_STATUS (Slave preparing data, should read N times)
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* 3. Read DATA ()
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*/
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#define MEM_CMD_WRITE 0x10
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#define MEM_CMD_LOAD 0x20
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#define MEM_CMD_STATUS 0x21
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#define MEM_CMD_READ 0x22
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#define WRITE_STATUS_VAL 0xF0F0F0F0
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#define LOAD_STATUS_VAL 0xF1F1F1F1
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#define TEST_BUF_SIZE (512 * 1024)
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/* All data should be 4 bytes aligned. */
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#define CMD_SIZE 4
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#define STATUS_SIZE 4
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// #define PKT_SIZE TEST_BUF_SIZE
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#define PKT_SIZE 256
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int test_qspi_slave_controller_init(u32 id, u32 bus_width,
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qspi_slave_async_cb cb, void *priv,
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qspi_slave_handle *h);
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void test_qspi_slave_controller_deinit(qspi_slave_handle *h);
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#endif
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