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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-17 03:48:55 +00:00
397 lines
10 KiB
C
397 lines
10 KiB
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: geo <guojun.dong@artinchip.com>
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*/
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#include <rtconfig.h>
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#include <stdbool.h>
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#include <string.h>
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#include <hal_i2c.h>
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#include "aic_errno.h"
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#define gen_reg(val) (volatile void *)(val)
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#define USEC_PER_SEC (1000000)
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int hal_i2c_clk_init(aic_i2c_ctrl *i2c_dev)
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{
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int ret = 0;
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ret = hal_clk_enable_deassertrst(CLK_I2C0 + i2c_dev->index);
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if (ret < 0)
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pr_err("I2C clock and reset init error\n");
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return ret;
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}
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void hal_i2c_set_hold(aic_i2c_ctrl *i2c_dev, u32 val)
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{
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writel(val, i2c_dev->reg_base + I2C_SDA_HOLD);
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}
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int hal_i2c_set_master_slave_mode(aic_i2c_ctrl *i2c_dev)
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{
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uint32_t reg_val;
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uint8_t mode;
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CHECK_PARAM(i2c_dev, -EINVAL);
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mode = i2c_dev->bus_mode;
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reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_MASTER_SLAVE_SELECT_MASK;
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if (!mode)
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reg_val |= I2C_ENABLE_MASTER_DISABLE_SLAVE;
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else
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/* slave mode, and will detect stop signal only if addressed */
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reg_val |= I2C_CTL_STOP_DET_IFADDR;
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writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
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return 0;
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}
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int hal_i2c_master_10bit_addr(aic_i2c_ctrl *i2c_dev)
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{
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uint32_t reg_val;
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uint8_t enable;
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CHECK_PARAM(i2c_dev, -EINVAL);
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enable = i2c_dev->addr_bit;
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reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_10BIT_SELECT_MASTER;
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if (enable)
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reg_val |= I2C_CTL_10BIT_SELECT_MASTER;
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writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
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return 0;
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}
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int hal_i2c_slave_10bit_addr(aic_i2c_ctrl *i2c_dev)
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{
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uint32_t reg_val;
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uint8_t enable;
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CHECK_PARAM(i2c_dev, -EINVAL);
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enable = i2c_dev->addr_bit;
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reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_10BIT_SELECT_SLAVE;
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if (enable)
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reg_val |= I2C_CTL_10BIT_SELECT_SLAVE;
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writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
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return 0;
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}
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static int hal_i2c_scl_cnt(uint32_t clk_freq, uint8_t is_standard_speed,
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uint16_t *hcnt, uint16_t *lcnt)
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{
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uint16_t hcnt_tmp, lcnt_tmp;
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CHECK_PARAM(hcnt, -EINVAL);
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CHECK_PARAM(lcnt, -EINVAL);
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if (is_standard_speed) {
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/* Minimum value of tHIGH in standard mode is 4000ns
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* Plus 2 is just to increase the time of tHIGH, appropriately.
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* SS_MIN_SCL_HIGH * (clk_freq / 1000) is just to prevent 32bits
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* overflow. SS_MIN_SCL_HIGH * clk_freq will 32bits overflow.
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*/
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hcnt_tmp = SS_MIN_SCL_HIGH * (clk_freq / 1000) / 1000000 + 2;
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lcnt_tmp = SS_MIN_SCL_LOW * (clk_freq / 1000) / 1000000 + 2;
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} else {
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/* If isStandardSpeed is false, set i2c to fast speed
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* Minimum value of tHIGH in fast mode is 600ns
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* Plus 3 is just to increase the time of tHIGH, appropriately.
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* FS_MIN_SCL_HIGH * (clk_freq / 1000)
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*/
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hcnt_tmp = FS_MIN_SCL_HIGH * (clk_freq / 1000) / 1000000 + 2;
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lcnt_tmp = FS_MIN_SCL_LOW * (clk_freq / 1000) / 1000000 + 2;
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}
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*hcnt = hcnt_tmp;
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*lcnt = lcnt_tmp;
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return 0;
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}
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int hal_i2c_speed_mode_select(aic_i2c_ctrl *i2c_dev, uint32_t clk_freq, uint8_t mode)
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{
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uint32_t reg_val;
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uint16_t hcnt, lcnt;
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int ret;
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CHECK_PARAM(i2c_dev, -EINVAL);
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reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_SPEED_MODE_SELECT_MASK;
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if (!mode) {
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reg_val |= I2C_CTL_SPEED_MODE_FS;
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/* Calculate fast speed HCNT and LCNT */
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ret = hal_i2c_scl_cnt(clk_freq, false, &hcnt, &lcnt);
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if (ret)
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return ret;
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writel(hcnt, gen_reg(i2c_dev->reg_base + I2C_FS_SCL_HCNT));
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writel(lcnt, gen_reg(i2c_dev->reg_base + I2C_FS_SCL_LCNT));
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} else {
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reg_val |= I2C_CTL_SPEED_MODE_SS;
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/* Calculate standard speed HCNT and LCNT */
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ret = hal_i2c_scl_cnt(clk_freq, true, &hcnt, &lcnt);
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if (ret)
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return ret;
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writel(hcnt, gen_reg(i2c_dev->reg_base + I2C_SS_SCL_HCNT));
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writel(lcnt, gen_reg(i2c_dev->reg_base + I2C_SS_SCL_LCNT));
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}
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writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_CTL));
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return 0;
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}
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void hal_i2c_target_addr(aic_i2c_ctrl *i2c_dev, uint32_t addr)
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{
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uint32_t reg_val;
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reg_val = readl(gen_reg(i2c_dev->reg_base + I2C_TAR));
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reg_val &= ~I2C_TAR_ADDR_MASK;
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reg_val |= addr;
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writel(reg_val, gen_reg(i2c_dev->reg_base + I2C_TAR));
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}
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int hal_i2c_slave_own_addr(aic_i2c_ctrl *i2c_dev, uint32_t addr)
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{
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CHECK_PARAM(i2c_dev, -EINVAL);
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CHECK_PARAM(!(addr > I2C_TAR_ADDR_MASK), -EINVAL);
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writel(addr, gen_reg(i2c_dev->reg_base + I2C_SAR));
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return 0;
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}
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int hal_i2c_init(aic_i2c_ctrl *i2c_dev)
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{
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int32_t ret = I2C_OK;
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ret = hal_i2c_clk_init(i2c_dev);
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if (ret)
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return ret;
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hal_i2c_set_master_slave_mode(i2c_dev);
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hal_i2c_set_hold(i2c_dev, 10);
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hal_i2c_master_10bit_addr(i2c_dev);
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hal_i2c_slave_10bit_addr(i2c_dev);
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#ifdef AIC_I2C_INTERRUPT_MODE
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hal_i2c_disable_all_irq(i2c_dev);
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hal_i2c_set_transmit_fifo_threshold(i2c_dev);
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#else
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hal_i2c_master_enable_irq(i2c_dev);
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#endif
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ret = hal_i2c_speed_mode_select(i2c_dev, I2C_DEFALT_CLOCK, i2c_dev->speed_mode);
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if (ret)
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return ret;
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if (i2c_dev->bus_mode) {
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hal_i2c_config_fifo_slave(i2c_dev);
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hal_i2c_clear_all_irq_flags(i2c_dev);
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hal_i2c_slave_enable_irq(i2c_dev);
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hal_i2c_module_disable(i2c_dev);
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hal_i2c_slave_own_addr(i2c_dev, i2c_dev->slave_addr);
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hal_i2c_module_enable(i2c_dev);
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}
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return ret;
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}
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static int32_t hal_i2c_wait_transmit(aic_i2c_ctrl *i2c_dev, uint32_t timeout)
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{
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int32_t ret = I2C_OK;
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do {
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uint64_t timecount = timeout + aic_get_time_ms();
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while ((hal_i2c_get_transmit_fifo_num(i2c_dev) != 0U) &&
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(ret == EOK)) {
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if (aic_get_time_ms() >= timecount) {
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ret = I2C_TIMEOUT;
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}
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}
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} while (0);
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return ret;
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}
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static int32_t hal_i2c_wait_receive(aic_i2c_ctrl *i2c_dev,
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uint32_t wait_data_num, uint32_t timeout)
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{
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int32_t ret = I2C_OK;
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do {
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uint64_t timecount = timeout + aic_get_time_ms();
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while ((hal_i2c_get_receive_fifo_num(i2c_dev) < wait_data_num) &&
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(ret == I2C_OK)) {
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if (aic_get_time_ms() >= timecount) {
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ret = I2C_TIMEOUT;
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}
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}
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} while (0);
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return ret;
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}
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int32_t hal_i2c_wait_bus_free(aic_i2c_ctrl *i2c_dev, uint32_t timeout)
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{
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int32_t ret = I2C_OK;
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uint64_t timecount = timeout + aic_get_time_ms();
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while (hal_i2c_bus_status(i2c_dev)) {
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if (aic_get_time_ms() >= timecount) {
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ret = I2C_TIMEOUT;
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return ret;
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}
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}
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return ret;
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}
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/**
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\brief hal_i2c_master_send_msg
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\param[in] reg_base
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\param[in]
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\return bytes of sent msg
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*/
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int32_t hal_i2c_master_send_msg(aic_i2c_ctrl *i2c_dev,
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struct aic_i2c_msg *msg, uint8_t is_last_message)
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{
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CHECK_PARAM(msg, -EINVAL);
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int32_t ret = I2C_OK;
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uint16_t size = msg->len;
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uint32_t send_count = 0;
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uint32_t stop_time = 0;
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uint32_t timeout = 10;
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uint32_t reg_val;
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uint16_t idx = 0;
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hal_i2c_module_disable(i2c_dev);
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hal_i2c_target_addr(i2c_dev, msg->addr);
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hal_i2c_module_enable(i2c_dev);
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if (!size)
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{
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hal_i2c_transmit_data_with_stop_bit(i2c_dev, 0);
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while (1)
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{
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reg_val = readl(i2c_dev->reg_base + I2C_INTR_RAW_STAT);
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if (reg_val & I2C_INTR_STOP_DET)
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{
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if (reg_val & I2C_INTR_TX_ABRT)
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{
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return -1;
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}
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else
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{
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return 0;
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}
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}
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}
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}
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while (size > 0) {
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uint16_t send_num = size > I2C_FIFO_DEPTH ? I2C_FIFO_DEPTH : size;
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for (uint16_t i = 0; i < send_num; i++) {
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if (is_last_message && (idx == msg->len -1))
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hal_i2c_transmit_data_with_stop_bit(i2c_dev, msg->buf[idx]);
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else if (!is_last_message && (idx == 0))
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hal_i2c_set_restart_bit_with_data(i2c_dev, msg->buf[idx]);
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else
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hal_i2c_transmit_data(i2c_dev, msg->buf[idx]);
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idx++;
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}
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size -= send_num;
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send_count += send_num;
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ret = hal_i2c_wait_transmit(i2c_dev, timeout);
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if (ret != I2C_OK) {
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send_count = ret;
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return I2C_TIMEOUT;
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}
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}
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while (!(hal_i2c_get_raw_interrupt_state(i2c_dev)
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& (I2C_INTR_STOP_DET | I2C_INTR_START_DET))) {
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stop_time++;
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if (stop_time > I2C_TIMEOUT_DEF_VAL) {
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return I2C_TIMEOUT;
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}
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}
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return send_count;
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}
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/**
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\brief hal_i2c_master_receive_msg
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\param[in] reg_base
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\param[in]
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\return bytes of read msg
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*/
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int32_t hal_i2c_master_receive_msg(aic_i2c_ctrl *i2c_dev,
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struct aic_i2c_msg *msg, uint8_t is_last_message)
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{
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CHECK_PARAM(msg, -EINVAL);
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int32_t ret = I2C_OK;
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uint16_t size = msg->len;
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uint32_t read_count = 0;
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uint8_t *receive_data = msg->buf;
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uint32_t timeout = 10;
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int idx = 0, count = 0;
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CHECK_PARAM(receive_data, -EINVAL);
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hal_i2c_module_disable(i2c_dev);
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hal_i2c_target_addr(i2c_dev, msg->addr);
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hal_i2c_module_enable(i2c_dev);
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while (size > 0) {
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int32_t recv_num = size > I2C_FIFO_DEPTH ? I2C_FIFO_DEPTH : size;
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for (uint16_t len = 0; len < recv_num; len++) {
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if (is_last_message && (count == msg->len - 1))
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hal_i2c_read_data_cmd_with_stop_bit(i2c_dev);
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else
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hal_i2c_read_data_cmd(i2c_dev);
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count++;
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}
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size -= recv_num;
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read_count += recv_num;
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ret = hal_i2c_wait_receive(i2c_dev, recv_num, timeout);
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if (ret == I2C_OK) {
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for (uint16_t i = 0; i < recv_num; i++) {
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receive_data[idx] = hal_i2c_get_receive_data(i2c_dev);
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idx++;
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}
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} else {
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read_count = (int32_t)ret;
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break;
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}
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}
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uint32_t timecount = timeout + aic_get_time_ms();
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while (!(hal_i2c_get_raw_interrupt_state(i2c_dev)
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& (I2C_INTR_STOP_DET | I2C_INTR_START_DET))) {
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if (aic_get_time_ms() >= timecount) {
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return I2C_TIMEOUT;
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break;
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}
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}
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return read_count;
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}
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