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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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265 lines
6.9 KiB
C
265 lines
6.9 KiB
C
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ARTINCHIP_AIC_CLK_ID_H__
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#define __ARTINCHIP_AIC_CLK_ID_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum clk_id {
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/* Fixed rate clock */
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CLK_DUMMY,
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CLK_OSC24M,
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CLK_OSC32K,
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/* PLL clock */
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CLK_PLL_INT0,
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CLK_PLL_INT1,
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CLK_PLL_FRA0,
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CLK_PLL_FRA2,
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/* fixed factor clock */
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CLK_AXI_AHB_SRC1,
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CLK_APB0_SRC1,
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CLK_CPU_SRC1,
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/* system clock */
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CLK_AXI0,
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CLK_AHB0,
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CLK_APB0,
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CLK_APB1,
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CLK_CPU,
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/* Peripheral clock */
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CLK_WDT,
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CLK_DMA,
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CLK_CE,
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CLK_USBD,
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CLK_USBH0,
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CLK_USB_PHY0,
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CLK_GMAC0,
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CLK_XSPI,
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CLK_QSPI0,
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CLK_QSPI1,
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CLK_QSPI2,
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CLK_QSPI3,
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CLK_SDMC0,
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CLK_SDMC1,
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CLK_PBUS,
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CLK_SYSCFG,
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CLK_SPIENC,
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CLK_MTOP,
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CLK_I2S0,
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CLK_AUDIO_SCLK,
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CLK_CODEC,
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CLK_GPIO,
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CLK_UART0,
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CLK_UART1,
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CLK_UART2,
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CLK_UART3,
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CLK_UART4,
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CLK_UART5,
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CLK_UART6,
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CLK_UART7,
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CLK_RGB,
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CLK_LVDS,
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CLK_MIPIDSI,
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CLK_DVP,
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CLK_DE,
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CLK_GE,
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CLK_VE,
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CLK_SID,
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CLK_RTC,
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CLK_GTC,
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CLK_I2C0,
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CLK_I2C1,
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CLK_I2C2,
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CLK_CAN0,
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CLK_CAN1,
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CLK_PWM,
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CLK_ADCIM,
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CLK_GPAI,
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CLK_RTP,
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CLK_TSEN,
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CLK_CIR,
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CLK_PSADC,
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CLK_CMP,
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CLK_PWMCS,
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CLK_PWMCS_SDFM,
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/* Display clock */
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CLK_PIX,
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CLK_SCLK,
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/* Output clock */
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CLK_OUT0,
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CLK_OUT1,
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CLK_OUT2,
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CLK_OUT3,
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AIC_CLK_NUM,
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};
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/* frequence */
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#define CLOCK1_FREQ 48000000
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#define CLOCK2_FREQ 60000000
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#define CLOCK3_FREQ 120000000
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#define CLOCK4_FREQ 62500000
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#define CLOCK5_FREQ 48000000
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#define CLOCK6_FREQ 60000000
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#define CLOCK_120M 120000000
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#define CLOCK_100M 100000000
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#define CLOCK_72M 72000000
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#define CLOCK_60M 60000000
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#define CLOCK_50M 50000000
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#define CLOCK_36M 36000000
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#define CLOCK_30M 30000000
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#define CLOCK_AUDIO 24576000
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#define CLOCK_24M 24000000
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#define CLOCK_12M 12000000
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#define CLOCK_4M 4000000
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#define CLOCK_1M 1000000
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#define CLOCK_32K 32768
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/*--- ArtInChip CMU register offsets ---*/
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#define PLL_INT0_GEN_REG (0x0000)
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#define PLL_INT1_GEN_REG (0x0004)
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#define PLL_FRA0_GEN_REG (0x0020)
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#define PLL_FRA2_GEN_REG (0x0028)
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#define PLL_INT0_CFG_REG (0x0040)
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#define PLL_INT1_CFG_REG (0x0044)
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#define PLL_FRA0_CFG_REG (0x0060)
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#define PLL_FRA2_CFG_REG (0x0068)
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#define PLL_FRA0_SDM_REG (0x0080)
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#define PLL_FRA2_SDM_REG (0x0088)
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#define PLL_COM_REG (0x00A0)
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#define PLL_IN_REG (0x00A4)
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#define CLK_OUT0_REG (0x00E0)
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#define CLK_OUT1_REG (0x00E4)
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#define CLK_OUT2_REG (0x00E8)
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#define CLK_OUT3_REG (0x00EC)
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#define CLK_AXI_AHB_REG (0x0100)
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#define CLK_APB0_REG (0x0120)
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#define CLK_APB1_REG (0x0124)
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#define CLK_CPU_REG (0x0200)
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#define CLK_DM_REG (0x0204)
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#define CLK_WDT_REG (0x020C)
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#define CLK_DISP_REG (0x0220)
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#define CLK_AUDIO_REG (0x0230)
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#define CLK_PWMCS_SDFM_REG (0x0240)
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#define CLK_DMA_REG (0x0410)
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#define CLK_CE_REG (0x0418)
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#define CLK_USBD_REG (0x041C)
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#define CLK_USBH0_REG (0x0420)
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#define CLK_USB_PHY0_REG (0x0430)
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#define CLK_GMAC0_REG (0x0440)
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#define CLK_XSPI_REG (0x045C)
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#define CLK_QSPI0_REG (0x0460)
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#define CLK_QSPI1_REG (0x0464)
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#define CLK_QSPI2_REG (0x0468)
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#define CLK_QSPI3_REG (0x046C)
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#define CLK_SDMC0_REG (0x0470)
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#define CLK_SDMC1_REG (0x0474)
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#define CLK_CORDIC_REG (0x0490)
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#define CLK_HCL_REG (0x0490)
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#define CLK_PBUS_REG (0x04A0)
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#define CLK_SYSCFG_REG (0x0800)
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#define CLK_SPIENC_REG (0x0810)
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#define CLK_PWMCS_REG (0x0814)
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#define CLK_PSADC_REG (0x0818)
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#define CLK_MTOP_REG (0x081C)
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#define CLK_I2S0_REG (0x0820)
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#define CLK_CODEC_REG (0x0830)
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#define CLK_GPIO_REG (0x083C)
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#define CLK_UART0_REG (0x0840)
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#define CLK_UART1_REG (0x0844)
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#define CLK_UART2_REG (0x0848)
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#define CLK_UART3_REG (0x084C)
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#define CLK_UART4_REG (0x0850)
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#define CLK_UART5_REG (0x0854)
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#define CLK_UART6_REG (0x0858)
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#define CLK_UART7_REG (0x085C)
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#define CLK_TA_IF_REG (0x0870)
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#define CLK_EDT_REG (0x0874)
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#define CLK_BISS_IF_REG (0x0878)
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#define CLK_SDFM_REG (0x087C)
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#define CLK_RGB_REG (0x0880)
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#define CLK_LVDS_REG (0x0884)
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#define CLK_MIPID_REG (0x0888)
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#define CLK_DVP_REG (0x0890)
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#define CLK_DE_REG (0x08C0)
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#define CLK_GE_REG (0x08C4)
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#define CLK_VE_REG (0x08C8)
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#define CLK_SID_REG (0x0904)
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#define CLK_RTC_REG (0x0908)
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#define CLK_GTC_REG (0x090C)
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#define CLK_I2C0_REG (0x0960)
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#define CLK_I2C1_REG (0x0964)
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#define CLK_I2C2_REG (0x0968)
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#define CLK_CAN0_REG (0x0980)
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#define CLK_CAN1_REG (0x0984)
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#define CLK_PWM_REG (0x0990)
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#define CLK_ADCIM_REG (0x09A0)
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#define CLK_GPAI_REG (0x09A4)
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#define CLK_RTP_REG (0x09A8)
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#define CLK_TSEN_REG (0x09AC)
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#define CLK_CIR_REG (0x09B0)
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#define CLK_CMP_REG (0x09E4)
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#define CLK_VER_REG (0x0FFC)
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/* PLL_xxx_GEN register fields */
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#define PLL_LOCK_BIT (17)
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#define PLL_EN_BIT (16)
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#define PLL_FACTORN_BIT (8)
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#define PLL_FACTORN_MASK (0xff)
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#define PLL_FACTORN_MIN (14)
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#define PLL_FACTORN_MAX (199)
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#define PLL_FACTORM_BIT (4)
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#define PLL_FACTORM_MASK (0x3)
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#define PLL_FACTORM_MIN (0)
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#define PLL_FACTORM_MAX (3)
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#define PLL_FACTORM_EN_BIT (19)
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#define PLL_FACTORP_BIT (0)
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#define PLL_FACTORP_MASK (0x1)
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#define PLL_FACTORP_MIN (0)
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#define PLL_FACTORP_MAX (1)
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#define PLL_DITHER_EN_BIT (24)
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#define PLL_FRAC_EN_BIT (20)
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#define PLL_FRAC_DIV_BIT (0)
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#define PLL_FRAC_DIV_MASK (0x1ffff)
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#define PLL_OUT_MUX (20)
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#define PLL_OUT_SYS (18)
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#define PLL_SDM_AMP_BIT (0)
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#define PLL_SDM_FREQ_BIT (17)
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#define PLL_SDM_STEP_BIT (20)
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#define PLL_SDM_MODE_BIT (29)
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#define PLL_SDM_EN_BIT (31)
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#define PLL_VCO_MIN (768000000)
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#define PLL_VCO_MAX (1560000000)
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#define PLL_SDM_AMP_MAX (0x20000)
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#define PLL_SDM_SPREAD_PPM (10000)
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#define PLL_SDM_SPREAD_FREQ (33000)
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/* BUS CLX_xxx register fields */
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#define BUS_CLK_SEL (8)
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/* APB0 CLX_xxx register fields */
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#define MOD_RSTN (13)
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#define MOD_BUS_EN (12)
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#define MOD_CLK_EN (8)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ARTINCHIP_AIC_CLK_ID_H__ */
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