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47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
/*
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* Copyright (c) 2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Mingfeng.Li <mingfeng.li@artinchip.com>
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*/
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#include <rtconfig.h>
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#include <stdbool.h>
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#include <string.h>
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#include <stdint.h>
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#include <aic_common.h>
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#include <aic_core.h>
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#include <aic_hal.h>
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#include <hal_dma.h>
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#include <hal_axicfg.h>
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#include "axicfg_hw_v1.0.h"
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#include "aic_hal_reset.h"
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int hal_axicfg_module_wr_init(u8 mode, hal_axicfg_port_t device_p, u8 priority)
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{
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// read: mode = 0; write: mode = 1;
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axicfg_hw_cfg0_set_reulator_en(HAL_AXICFG_BASE, mode, (u8)device_p, 0);
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axicfg_hw_cfg0_set_slv_ready(HAL_AXICFG_BASE, mode, (u8)device_p, 0);
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axicfg_hw_cfg0_set_burst_limit(HAL_AXICFG_BASE, mode, (u8)device_p, 0);
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axicfg_hw_cfg0_set_qos_sel(HAL_AXICFG_BASE, mode, (u8)device_p, HAL_AXICFG_INT_QOS);
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axicfg_hw_cfg0_set_qos_val(HAL_AXICFG_BASE, mode, (u8)device_p, priority);
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axicfg_hw_cfg1_set_basic_rate(HAL_AXICFG_BASE, mode, (u8)device_p, 0);
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axicfg_hw_cfg1_set_burst_rate(HAL_AXICFG_BASE, mode, (u8)device_p, 0);
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return 0;
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}
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int hal_axicfg_module_init(hal_axicfg_port_t device_p, u8 priority)
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{
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u8 mode = 0;
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for (mode = 0; mode < 2; mode++) {
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// read: mode = 0; write: mode = 1;
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hal_axicfg_module_wr_init(mode, device_p, priority);
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}
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return 0;
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}
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