mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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131 lines
2.7 KiB
C
131 lines
2.7 KiB
C
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <aic_core.h>
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#include <aic_drv_irq.h>
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#include <aic_hal.h>
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extern void drv_irq_vectors_init(void);
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extern void mm_heap_initialize(void);
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int SystemCoreClock = IHS_VALUE; /* System Core Clock Frequency */
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extern int __Vectors;
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void SystemCoreClockUpdate(void)
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{
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SystemCoreClock = IHS_VALUE;
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}
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#ifndef QEMU_RUN
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void aic_clk_lowpower(void)
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{
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hal_clk_pll_lowpower();
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hal_clk_disable_assertrst(CLK_USB_PHY0);
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hal_clk_disable_assertrst(CLK_USBH0);
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hal_clk_disable_assertrst(CLK_USBD);
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hal_clk_disable_assertrst(CLK_USB_PHY1);
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hal_clk_disable_assertrst(CLK_USBH1);
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}
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void aic_gtc_enable(void)
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{
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/* enable gtc clk */
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*(volatile uint32_t *)(CMU_BASE+0x090c) = 0x3100;
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/* enable gtc */
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*(volatile uint32_t *)GTC_BASE = 0x0001;
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}
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#endif
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void dcache_enable(void)
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{
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aicos_dcache_enable();
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}
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void icache_enable(void)
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{
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aicos_icache_enable();
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}
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static void _system_init_for_kernel(void)
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{
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drv_irq_vectors_init();
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#ifndef QEMU_RUN
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aic_clk_lowpower();
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aic_gtc_enable();
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#endif
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csi_plic_set_prio(PLIC_BASE, CORET_IRQn, 31U);
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csi_clint_config(CORET_BASE, (drv_get_sys_freq() / CONFIG_SYSTICK_HZ), CORET_IRQn);
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drv_irq_enable(CORET_IRQn);
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}
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static void interrupt_init(void)
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{
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int i;
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for (i = 0; i < 1023; i++) {
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PLIC->PLIC_PRIO[i] = 31;
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}
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for (i = 0; i < 32; i++) {
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PLIC->PLIC_IP[i] = 0;
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}
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for (i = 0; i < 32; i++) {
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PLIC->PLIC_H0_MIE[i] = 0;
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PLIC->PLIC_H0_SIE[i] = 0;
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}
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/* set hart threshold 0, enable all interrupt */
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PLIC->PLIC_H0_MTH = 0;
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PLIC->PLIC_H0_STH = 0;
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for (i = 0; i < 1023; i++) {
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PLIC->PLIC_H0_MCLAIM = i;
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PLIC->PLIC_H0_SCLAIM = i;
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}
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/* set PLIC_PER */
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PLIC->PLIC_PER = 0x1;
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/* enable msoft interrupt ; Machine_Software_IRQn*/
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uint64_t mie = __get_MIE();
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mie |= (1 << 11 | 1 << 7 | 1 << 3);
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__set_MIE(mie);
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}
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/**
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* @brief initialize the system
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* Initialize the psr and vbr.
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* @param None
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* @return None
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*/
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void SystemInit(void)
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{
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/* enable mstatus FS & VS */
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#ifdef ARCH_RISCV_FPU
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uint64_t mstatus = __get_MSTATUS();
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mstatus &= ~(0x3UL << 13);
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mstatus |= (0x1UL << 13);
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mstatus &= ~(0x3UL << 23);
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mstatus |= (0x1UL << 23);
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__set_MSTATUS(mstatus);
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#endif
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/* enable mxstatus THEADISAEE */
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uint64_t mxstatus = __get_MXSTATUS();
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mxstatus |= (1 << 22);
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/* enable mxstatus MM */
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mxstatus |= (1 << 15);
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__set_MXSTATUS(mxstatus);
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interrupt_init();
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drv_irq_enable(Machine_Software_IRQn);
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_system_init_for_kernel();
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}
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