mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-15 02:48:54 +00:00
597 lines
18 KiB
C
597 lines
18 KiB
C
/*
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* Change Logs
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* Date Author Notes
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* 2022-04-17 aozima the first version for CherryUSB.
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*/
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#ifndef __LINUX_USBNET_ASIX_H
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#define __LINUX_USBNET_ASIX_H
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// #define __BIG_ENDIAN_BITFIELD
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#define __LITTLE_ENDIAN_BITFIELD
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typedef uint8_t u8;
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typedef uint16_t u16;
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typedef uint32_t u32;
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#define KERNEL_VERSION(...) (0)
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#define LINUX_VERSION_CODE (1)
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/*
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* Turn on this flag if the implementation of your USB host controller
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* cannot handle non-double word aligned buffer.
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* When turn on this flag, driver will fixup egress packet aligned on double
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* word boundary before deliver to USB host controller. And will Disable the
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* function "skb_reserve (skb, NET_IP_ALIGN)" to retain the buffer aligned on
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* double word alignment for ingress packets.
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*/
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#define AX_FORCE_BUFF_ALIGN 0
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//#define RX_SKB_COPY
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#define AX_MONITOR_MODE 0x01
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#define AX_MONITOR_LINK 0x02
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#define AX_MONITOR_MAGIC 0x04
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#define AX_MONITOR_HSFS 0x10
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/* AX88172 Medium Status Register values */
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#define AX_MEDIUM_FULL_DUPLEX 0x02
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#define AX_MEDIUM_TX_ABORT_ALLOW 0x04
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#define AX_MEDIUM_FLOW_CONTROL_EN 0x10
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#define AX_MCAST_FILTER_SIZE 8
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#define AX_MAX_MCAST 64
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#define AX_EEPROM_LEN 0x40
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#define AX_SWRESET_CLEAR 0x00
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#define AX_SWRESET_RR 0x01
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#define AX_SWRESET_RT 0x02
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#define AX_SWRESET_PRTE 0x04
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#define AX_SWRESET_PRL 0x08
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#define AX_SWRESET_BZ 0x10
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#define AX_SWRESET_IPRL 0x20
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#define AX_SWRESET_IPPD 0x40
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#define AX_SWRESET_IPOSC 0x0080
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#define AX_SWRESET_IPPSL_0 0x0100
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#define AX_SWRESET_IPPSL_1 0x0200
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#define AX_SWRESET_IPCOPS 0x0400
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#define AX_SWRESET_IPCOPSC 0x0800
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#define AX_SWRESET_AUTODETACH 0x1000
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#define AX_SWRESET_WOLLP 0x8000
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#define AX88772_IPG0_DEFAULT 0x15
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#define AX88772_IPG1_DEFAULT 0x0c
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#define AX88772_IPG2_DEFAULT 0x0E
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#define AX88772A_IPG0_DEFAULT 0x15
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#define AX88772A_IPG1_DEFAULT 0x16
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#define AX88772A_IPG2_DEFAULT 0x1A
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#define AX88772_MEDIUM_FULL_DUPLEX 0x0002
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#define AX88772_MEDIUM_RESERVED 0x0004
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#define AX88772_MEDIUM_RX_FC_ENABLE 0x0010
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#define AX88772_MEDIUM_TX_FC_ENABLE 0x0020
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#define AX88772_MEDIUM_PAUSE_FORMAT 0x0080
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#define AX88772_MEDIUM_RX_ENABLE 0x0100
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#define AX88772_MEDIUM_100MB 0x0200
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#define AX88772_MEDIUM_DEFAULT \
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(AX88772_MEDIUM_FULL_DUPLEX | AX88772_MEDIUM_RX_FC_ENABLE | \
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AX88772_MEDIUM_TX_FC_ENABLE | AX88772_MEDIUM_100MB | \
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AX88772_MEDIUM_RESERVED | AX88772_MEDIUM_RX_ENABLE)
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#define AX_CMD_SET_SW_MII 0x06
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#define AX_CMD_READ_MII_REG 0x07
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#define AX_CMD_WRITE_MII_REG 0x08
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#define AX_CMD_READ_STATMNGSTS_REG 0x09
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#define AX_HOST_EN 0x01
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#define AX_CMD_SET_HW_MII 0x0a
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#define AX_CMD_READ_EEPROM 0x0b
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#define AX_CMD_WRITE_EEPROM 0x0c
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#define AX_CMD_WRITE_EEPROM_EN 0x0d
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#define AX_CMD_WRITE_EEPROM_DIS 0x0e
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#define AX_CMD_WRITE_RX_CTL 0x10
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#define AX_CMD_READ_IPG012 0x11
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#define AX_CMD_WRITE_IPG0 0x12
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#define AX_CMD_WRITE_IPG1 0x13
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#define AX_CMD_WRITE_IPG2 0x14
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#define AX_CMD_WRITE_MULTI_FILTER 0x16
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#define AX_CMD_READ_NODE_ID 0x17
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#define AX_CMD_READ_PHY_ID 0x19
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#define AX_CMD_READ_MEDIUM_MODE 0x1a
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#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
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#define AX_CMD_READ_MONITOR_MODE 0x1c
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#define AX_CMD_WRITE_MONITOR_MODE 0x1d
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#define AX_CMD_WRITE_GPIOS 0x1f
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#define AX_CMD_SW_RESET 0x20
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#define AX_CMD_SW_PHY_STATUS 0x21
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#define AX_CMD_SW_PHY_SELECT 0x22
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#define AX_PHYSEL_PSEL (1 << 0)
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#define AX_PHYSEL_ASEL (1 << 1)
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#define AX_PHYSEL_SSMII (0 << 2)
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#define AX_PHYSEL_SSRMII (1 << 2)
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#define AX_PHYSEL_SSRRMII (3 << 2)
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#define AX_PHYSEL_SSEN (1 << 4)
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#define AX88772_CMD_READ_NODE_ID 0x13
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#define AX88772_CMD_WRITE_NODE_ID 0x14
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#define AX_CMD_READ_WKFARY 0x23
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#define AX_CMD_WRITE_WKFARY 0x24
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#define AX_CMD_READ_RXCOE_CTL 0x2b
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#define AX_CMD_WRITE_RXCOE_CTL 0x2c
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#define AX_CMD_READ_TXCOE_CTL 0x2d
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#define AX_CMD_WRITE_TXCOE_CTL 0x2e
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#define REG_LENGTH 2
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#define PHY_ID_MASK 0x1f
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#define AX_RXCOE_IPCE 0x0001
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#define AX_RXCOE_IPVE 0x0002
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#define AX_RXCOE_V6VE 0x0004
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#define AX_RXCOE_TCPE 0x0008
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#define AX_RXCOE_UDPE 0x0010
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#define AX_RXCOE_ICMP 0x0020
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#define AX_RXCOE_IGMP 0x0040
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#define AX_RXCOE_ICV6 0x0080
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#define AX_RXCOE_TCPV6 0x0100
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#define AX_RXCOE_UDPV6 0x0200
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#define AX_RXCOE_ICMV6 0x0400
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#define AX_RXCOE_IGMV6 0x0800
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#define AX_RXCOE_ICV6V6 0x1000
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#define AX_RXCOE_FOPC 0x8000
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)
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#define AX_RXCOE_DEF_CSUM (AX_RXCOE_IPCE | AX_RXCOE_IPVE | \
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AX_RXCOE_V6VE | AX_RXCOE_TCPE | \
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AX_RXCOE_UDPE | AX_RXCOE_ICV6 | \
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AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6)
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#else
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#define AX_RXCOE_DEF_CSUM (AX_RXCOE_IPCE | AX_RXCOE_IPVE | \
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AX_RXCOE_TCPE | AX_RXCOE_UDPE)
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#endif
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#define AX_RXCOE_64TE 0x0100
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#define AX_RXCOE_PPPOE 0x0200
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#define AX_RXCOE_RPCE 0x8000
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#define AX_TXCOE_IP 0x0001
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#define AX_TXCOE_TCP 0x0002
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#define AX_TXCOE_UDP 0x0004
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#define AX_TXCOE_ICMP 0x0008
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#define AX_TXCOE_IGMP 0x0010
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#define AX_TXCOE_ICV6 0x0020
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#define AX_TXCOE_TCPV6 0x0100
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#define AX_TXCOE_UDPV6 0x0200
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#define AX_TXCOE_ICMV6 0x0400
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#define AX_TXCOE_IGMV6 0x0800
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#define AX_TXCOE_ICV6V6 0x1000
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)
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#define AX_TXCOE_DEF_CSUM (AX_TXCOE_TCP | AX_TXCOE_UDP | \
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AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6)
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#else
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#define AX_TXCOE_DEF_CSUM (AX_TXCOE_TCP | AX_TXCOE_UDP)
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#endif
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#define AX_TXCOE_64TE 0x0001
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#define AX_TXCOE_PPPE 0x0002
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#define AX88772B_MAX_BULKIN_2K 0
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#define AX88772B_MAX_BULKIN_4K 1
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#define AX88772B_MAX_BULKIN_6K 2
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#define AX88772B_MAX_BULKIN_8K 3
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#define AX88772B_MAX_BULKIN_16K 4
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#define AX88772B_MAX_BULKIN_20K 5
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#define AX88772B_MAX_BULKIN_24K 6
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#define AX88772B_MAX_BULKIN_32K 7
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struct {unsigned short size, byte_cnt, threshold; } AX88772B_BULKIN_SIZE[] = {
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/* 2k */
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{2048, 0x8000, 0x8001},
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/* 4k */
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{4096, 0x8100, 0x8147},
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/* 6k */
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{6144, 0x8200, 0x81EB},
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/* 8k */
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{8192, 0x8300, 0x83D7},
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/* 16 */
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{16384, 0x8400, 0x851E},
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/* 20k */
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{20480, 0x8500, 0x8666},
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/* 24k */
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{24576, 0x8600, 0x87AE},
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/* 32k */
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{32768, 0x8700, 0x8A3D},
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};
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#define AX_RX_CTL_RH1M 0x0100 /* Enable RX-Header mode 0 */
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#define AX_RX_CTL_RH2M 0x0200 /* Enable IP header in receive buffer aligned on 32-bit aligment */
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#define AX_RX_CTL_RH3M 0x0400 /* checksum value in rx header 3 */
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#define AX_RX_HEADER_DEFAULT (AX_RX_CTL_RH1M | AX_RX_CTL_RH2M)
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#define AX_RX_CTL_MFB 0x0300 /* Maximum Frame size 16384bytes */
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#define AX_RX_CTL_START 0x0080 /* Ethernet MAC start */
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#define AX_RX_CTL_AP 0x0020 /* Accept physcial address from Multicast array */
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#define AX_RX_CTL_AM 0x0010
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#define AX_RX_CTL_AB 0x0008 /* Accetp Brocadcast frames*/
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#define AX_RX_CTL_SEP 0x0004 /* Save error packets */
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#define AX_RX_CTL_AMALL 0x0002 /* Accetp all multicast frames */
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#define AX_RX_CTL_PRO 0x0001 /* Promiscuous Mode */
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#define AX_RX_CTL_STOP 0x0000 /* Stop MAC */
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#define AX_MONITOR_MODE 0x01
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#define AX_MONITOR_LINK 0x02
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#define AX_MONITOR_MAGIC 0x04
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#define AX_MONITOR_HSFS 0x10
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#define AX_MCAST_FILTER_SIZE 8
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#define AX_MAX_MCAST 64
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#define AX_INTERRUPT_BUFSIZE 8
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#define AX_EEPROM_LEN 0x40
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#define AX_EEPROM_MAGIC 0xdeadbeef
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#define EEPROMMASK 0x7f
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/* GPIO REGISTER */
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#define AXGPIOS_GPO0EN 0X01 /* 1 << 0 */
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#define AXGPIOS_GPO0 0X02 /* 1 << 1 */
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#define AXGPIOS_GPO1EN 0X04 /* 1 << 2 */
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#define AXGPIOS_GPO1 0X08 /* 1 << 3 */
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#define AXGPIOS_GPO2EN 0X10 /* 1 << 4 */
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#define AXGPIOS_GPO2 0X20 /* 1 << 5 */
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#define AXGPIOS_RSE 0X80 /* 1 << 7 */
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/* TX-header format */
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#define AX_TX_HDR_CPHI 0x4000
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#define AX_TX_HDR_DICF 0x8000
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/* GMII register definitions */
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#define GMII_PHY_CONTROL 0x00 /* control reg */
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#define GMII_PHY_STATUS 0x01 /* status reg */
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#define GMII_PHY_OUI 0x02 /* most of the OUI bits */
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#define GMII_PHY_MODEL 0x03 /* model/rev bits, and rest of OUI */
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#define GMII_PHY_ANAR 0x04 /* AN advertisement reg */
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#define GMII_PHY_ANLPAR 0x05 /* AN Link Partner */
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#define GMII_PHY_ANER 0x06 /* AN expansion reg */
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#define GMII_PHY_1000BT_CONTROL 0x09 /* control reg for 1000BT */
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#define GMII_PHY_1000BT_STATUS 0x0A /* status reg for 1000BT */
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/* Bit definitions: GMII Control */
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#define GMII_CONTROL_RESET 0x8000 /* reset bit in control reg */
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#define GMII_CONTROL_LOOPBACK 0x4000 /* loopback bit in control reg */
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#define GMII_CONTROL_10MB 0x0000 /* 10 Mbit */
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#define GMII_CONTROL_100MB 0x2000 /* 100Mbit */
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#define GMII_CONTROL_1000MB 0x0040 /* 1000Mbit */
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#define GMII_CONTROL_SPEED_BITS 0x2040 /* speed bit mask */
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#define GMII_CONTROL_ENABLE_AUTO 0x1000 /* autonegotiate enable */
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#define GMII_CONTROL_POWER_DOWN 0x0800
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#define GMII_CONTROL_ISOLATE 0x0400 /* islolate bit */
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#define GMII_CONTROL_START_AUTO 0x0200 /* restart autonegotiate */
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#define GMII_CONTROL_FULL_DUPLEX 0x0100
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/* Bit definitions: GMII Status */
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#define GMII_STATUS_100MB_MASK 0xE000 /* any of these indicate 100 Mbit */
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#define GMII_STATUS_10MB_MASK 0x1800 /* either of these indicate 10 Mbit */
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#define GMII_STATUS_AUTO_DONE 0x0020 /* auto negotiation complete */
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#define GMII_STATUS_AUTO 0x0008 /* auto negotiation is available */
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#define GMII_STATUS_LINK_UP 0x0004 /* link status bit */
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#define GMII_STATUS_EXTENDED 0x0001 /* extended regs exist */
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#define GMII_STATUS_100T4 0x8000 /* capable of 100BT4 */
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#define GMII_STATUS_100TXFD 0x4000 /* capable of 100BTX full duplex */
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#define GMII_STATUS_100TX 0x2000 /* capable of 100BTX */
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#define GMII_STATUS_10TFD 0x1000 /* capable of 10BT full duplex */
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#define GMII_STATUS_10T 0x0800 /* capable of 10BT */
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/* Bit definitions: Auto-Negotiation Advertisement */
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#define GMII_ANAR_ASYM_PAUSE 0x0800 /* support asymetric pause */
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#define GMII_ANAR_PAUSE 0x0400 /* support pause packets */
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#define GMII_ANAR_100T4 0x0200 /* support 100BT4 */
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#define GMII_ANAR_100TXFD 0x0100 /* support 100BTX full duplex */
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#define GMII_ANAR_100TX 0x0080 /* support 100BTX half duplex */
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#define GMII_ANAR_10TFD 0x0040 /* support 10BT full duplex */
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#define GMII_ANAR_10T 0x0020 /* support 10BT half duplex */
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#define GMII_SELECTOR_FIELD 0x001F /* selector field. */
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/* Bit definitions: Auto-Negotiation Link Partner Ability */
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#define GMII_ANLPAR_100T4 0x0200 /* support 100BT4 */
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#define GMII_ANLPAR_100TXFD 0x0100 /* support 100BTX full duplex */
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#define GMII_ANLPAR_100TX 0x0080 /* support 100BTX half duplex */
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#define GMII_ANLPAR_10TFD 0x0040 /* support 10BT full duplex */
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#define GMII_ANLPAR_10T 0x0020 /* support 10BT half duplex */
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#define GMII_ANLPAR_PAUSE 0x0400 /* support pause packets */
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#define GMII_ANLPAR_ASYM_PAUSE 0x0800 /* support asymetric pause */
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#define GMII_ANLPAR_ACK 0x4000 /* means LCB was successfully rx'd */
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#define GMII_SELECTOR_8023 0x0001;
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/* Bit definitions: 1000BaseT AUX Control */
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#define GMII_1000_AUX_CTRL_MASTER_SLAVE 0x1000
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#define GMII_1000_AUX_CTRL_FD_CAPABLE 0x0200 /* full duplex capable */
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#define GMII_1000_AUX_CTRL_HD_CAPABLE 0x0100 /* half duplex capable */
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/* Bit definitions: 1000BaseT AUX Status */
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#define GMII_1000_AUX_STATUS_FD_CAPABLE 0x0800 /* full duplex capable */
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#define GMII_1000_AUX_STATUS_HD_CAPABLE 0x0400 /* half duplex capable */
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/* Cicada MII Registers */
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#define GMII_AUX_CTRL_STATUS 0x1C
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#define GMII_AUX_ANEG_CPLT 0x8000
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#define GMII_AUX_FDX 0x0020
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#define GMII_AUX_SPEED_1000 0x0010
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#define GMII_AUX_SPEED_100 0x0008
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#ifndef ADVERTISE_PAUSE_CAP
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#define ADVERTISE_PAUSE_CAP 0x0400
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#endif
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#ifndef MII_STAT1000
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#define MII_STAT1000 0x000A
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#endif
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#ifndef LPA_1000FULL
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#define LPA_1000FULL 0x0800
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#endif
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/* medium mode register */
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#define MEDIUM_GIGA_MODE 0x0001
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#define MEDIUM_FULL_DUPLEX_MODE 0x0002
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#define MEDIUM_TX_ABORT_MODE 0x0004
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#define MEDIUM_ENABLE_125MHZ 0x0008
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#define MEDIUM_ENABLE_RX_FLOWCTRL 0x0010
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#define MEDIUM_ENABLE_TX_FLOWCTRL 0x0020
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#define MEDIUM_ENABLE_JUMBO_FRAME 0x0040
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#define MEDIUM_CHECK_PAUSE_FRAME_MODE 0x0080
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#define MEDIUM_ENABLE_RECEIVE 0x0100
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#define MEDIUM_MII_100M_MODE 0x0200
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#define MEDIUM_ENABLE_JAM_PATTERN 0x0400
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#define MEDIUM_ENABLE_STOP_BACKPRESSURE 0x0800
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#define MEDIUM_ENABLE_SUPPER_MAC_SUPPORT 0x1000
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/* PHY mode */
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#define PHY_MODE_MARVELL 0
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#define PHY_MODE_CICADA_FAMILY 1
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#define PHY_MODE_CICADA_V1 1
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#define PHY_MODE_AGERE_FAMILY 2
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#define PHY_MODE_AGERE_V0 2
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#define PHY_MODE_CICADA_V2 5
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#define PHY_MODE_AGERE_V0_GMII 6
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#define PHY_MODE_CICADA_V2_ASIX 9
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#define PHY_MODE_VSC8601 10
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#define PHY_MODE_RTL8211CL 12
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#define PHY_MODE_RTL8211BN 13
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#define PHY_MODE_RTL8251CL 14
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#define PHY_MODE_ATTANSIC_V0 0x40
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#define PHY_MODE_ATTANSIC_FAMILY 0x40
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#define PHY_MODE_MAC_TO_MAC_GMII 0x7C
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/* */
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#define LED_MODE_MARVELL 0
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#define LED_MODE_CAMEO 1
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#define MARVELL_LED_CTRL 0x18
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#define MARVELL_MANUAL_LED 0x19
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#define PHY_IDENTIFIER 0x0002
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#define PHY_AGERE_IDENTIFIER 0x0282
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#define PHY_CICADA_IDENTIFIER 0x000f
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#define PHY_MARVELL_IDENTIFIER 0x0141
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#define PHY_MARVELL_STATUS 0x001b
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#define MARVELL_STATUS_HWCFG 0x0004 /* SGMII without clock */
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#define PHY_MARVELL_CTRL 0x0014
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#define MARVELL_CTRL_RXDELAY 0x0080
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#define MARVELL_CTRL_TXDELAY 0x0002
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#define PHY_CICADA_EXTPAGE 0x001f
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#define CICADA_EXTPAGE_EN 0x0001
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#define CICADA_EXTPAGE_DIS 0x0000
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/* External ethernet phy */
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#define EXTPHY_ID_MASK_OUI(phyid1, phyid2) ((phyid1 << 6) | ((phyid2 & 0xFC00) >> 10))
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#define EXTPHY_ID_MASK_MODEL(phyid2) ((phyid2 & 0x3F0) >> 4)
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#define EXTPHY_BROADCOM_OUI 0x2B8094
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#define EXTPHY_BCM89811_MODEL 0x02
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struct {unsigned short value, offset; } CICADA_FAMILY_HWINIT[] = {
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{0x0001, 0x001f}, {0x1c25, 0x0017}, {0x2a30, 0x001f}, {0x234c, 0x0010},
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{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0xa7fa, 0x0000},
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{0x0012, 0x0002}, {0x3002, 0x0001}, {0x87fa, 0x0000}, {0x52b5, 0x001f},
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{0xafac, 0x0000}, {0x000d, 0x0002}, {0x001c, 0x0001}, {0x8fac, 0x0000},
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{0x2a30, 0x001f}, {0x0012, 0x0008}, {0x2a30, 0x001f}, {0x0400, 0x0014},
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{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0xa760, 0x0000},
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{0x0000, 0x0002}, {0xfaff, 0x0001}, {0x8760, 0x0000}, {0x52b5, 0x001f},
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{0xa760, 0x0000}, {0x0000, 0x0002}, {0xfaff, 0x0001}, {0x8760, 0x0000},
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{0x52b5, 0x001f}, {0xafae, 0x0000}, {0x0004, 0x0002}, {0x0671, 0x0001},
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{0x8fae, 0x0000}, {0x2a30, 0x001f}, {0x0012, 0x0008}, {0x0000, 0x001f},
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};
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struct {unsigned short value, offset; } CICADA_V2_HWINIT[] = {
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{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0x000f, 0x0002},
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{0x472a, 0x0001}, {0x8fa4, 0x0000}, {0x2a30, 0x001f}, {0x0212, 0x0008},
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{0x0000, 0x001f},
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};
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struct {unsigned short value, offset; } CICADA_V2_ASIX_HWINIT[] = {
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{0x2a30, 0x001f}, {0x0212, 0x0008}, {0x52b5, 0x001f}, {0x0012, 0x0002},
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{0x3002, 0x0001}, {0x87fa, 0x0000}, {0x52b5, 0x001f}, {0x000f, 0x0002},
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{0x472a, 0x0001}, {0x8fa4, 0x0000}, {0x2a30, 0x001f}, {0x0212, 0x0008},
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{0x0000, 0x001f},
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};
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struct {unsigned short value, offset; } AGERE_FAMILY_HWINIT[] = {
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{0x0800, 0x0000}, {0x0007, 0x0012}, {0x8805, 0x0010}, {0xb03e, 0x0011},
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{0x8808, 0x0010}, {0xe110, 0x0011}, {0x8806, 0x0010}, {0xb03e, 0x0011},
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{0x8807, 0x0010}, {0xff00, 0x0011}, {0x880e, 0x0010}, {0xb4d3, 0x0011},
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{0x880f, 0x0010}, {0xb4d3, 0x0011}, {0x8810, 0x0010}, {0xb4d3, 0x0011},
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{0x8817, 0x0010}, {0x1c00, 0x0011}, {0x300d, 0x0010}, {0x0001, 0x0011},
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{0x0002, 0x0012},
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};
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struct ax88178_data {
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u16 EepromData;
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u16 MediaLink;
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int UseGpio0;
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int UseRgmii;
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u8 PhyMode;
|
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u8 LedMode;
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u8 BuffaloOld;
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};
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enum watchdog_state {
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AX_NOP = 0,
|
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CHK_LINK, /* Routine A */
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CHK_CABLE_EXIST, /* Called by A */
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CHK_CABLE_EXIST_AGAIN, /* Routine B */
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PHY_POWER_UP, /* Called by B */
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PHY_POWER_UP_BH,
|
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PHY_POWER_DOWN,
|
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CHK_CABLE_STATUS, /* Routine C */
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WAIT_AUTONEG_COMPLETE,
|
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AX_SET_RX_CFG,
|
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AX_CHK_AUTODETACH,
|
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};
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#if 0
|
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struct ax88772b_data {
|
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struct usbnet *dev;
|
|
struct workqueue_struct *ax_work;
|
|
struct work_struct check_link;
|
|
unsigned long time_to_chk;
|
|
u16 psc;
|
|
u8 pw_enabled;
|
|
u8 Event;
|
|
u8 checksum;
|
|
u8 PhySelect:1;
|
|
u8 OperationMode:1;
|
|
u16 presvd_phy_advertise;
|
|
u16 presvd_phy_bmcr;
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|
|
|
u32 ext_phy_oui;
|
|
u8 ext_phy_model;
|
|
};
|
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#endif
|
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|
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/* define for MAC or PHY mode */
|
|
#define OPERATION_MAC_MODE 0
|
|
#define OPERATION_PHY_MODE 1
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|
|
#if 0
|
|
struct ax88772a_data {
|
|
struct usbnet *dev;
|
|
struct workqueue_struct *ax_work;
|
|
struct work_struct check_link;
|
|
unsigned long autoneg_start;
|
|
#define AX88772B_WATCHDOG (6 * HZ)
|
|
u8 Event;
|
|
u8 TickToExpire;
|
|
u8 DlyIndex;
|
|
u8 DlySel;
|
|
u16 EepromData;
|
|
u16 presvd_phy_advertise;
|
|
u16 presvd_phy_bmcr;
|
|
};
|
|
|
|
struct ax88772_data {
|
|
struct usbnet *dev;
|
|
struct workqueue_struct *ax_work;
|
|
struct work_struct check_link;
|
|
unsigned long autoneg_start;
|
|
u8 Event;
|
|
u8 TickToExpire;
|
|
u16 presvd_phy_advertise;
|
|
u16 presvd_phy_bmcr;
|
|
};
|
|
#endif
|
|
|
|
#define AX_RX_CHECKSUM 1
|
|
#define AX_TX_CHECKSUM 2
|
|
|
|
#if 0
|
|
/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
|
|
struct ax8817x_data {
|
|
u8 multi_filter[AX_MCAST_FILTER_SIZE];
|
|
int (*resume) (struct usb_interface *intf);
|
|
int (*suspend) (struct usb_interface *intf,
|
|
#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 10)
|
|
pm_message_t message);
|
|
#else
|
|
u32 message);
|
|
#endif
|
|
};
|
|
#endif
|
|
|
|
struct ax88172_int_data {
|
|
u16 res1;
|
|
#define AX_INT_PPLS_LINK (1 << 0)
|
|
#define AX_INT_SPLS_LINK (1 << 1)
|
|
#define AX_INT_CABOFF_UNPLUG (1 << 7)
|
|
u8 link;
|
|
u16 res2;
|
|
u8 status;
|
|
u16 res3;
|
|
} __attribute__ ((packed));
|
|
|
|
#define AX_RXHDR_L4_ERR (1 << 8)
|
|
#define AX_RXHDR_L3_ERR (1 << 9)
|
|
|
|
#define AX_RXHDR_L4_TYPE_UDP 1
|
|
#define AX_RXHDR_L4_TYPE_ICMP 2
|
|
#define AX_RXHDR_L4_TYPE_IGMP 3
|
|
#define AX_RXHDR_L4_TYPE_TCP 4
|
|
#define AX_RXHDR_L4_TYPE_TCMPV6 5
|
|
#define AX_RXHDR_L4_TYPE_MASK 7
|
|
|
|
#define AX_RXHDR_L3_TYPE_IP 1
|
|
#define AX_RXHDR_L3_TYPE_IPV6 2
|
|
|
|
struct ax88772b_rx_header {
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
|
u16 len:11,
|
|
res1:1,
|
|
crc:1,
|
|
mii:1,
|
|
runt:1,
|
|
mc_bc:1;
|
|
|
|
u16 len_bar:11,
|
|
res2:5;
|
|
|
|
u8 vlan_ind:3,
|
|
vlan_tag_striped:1,
|
|
pri:3,
|
|
res3:1;
|
|
|
|
u8 l4_csum_err:1,
|
|
l3_csum_err:1,
|
|
l4_type:3,
|
|
l3_type:2,
|
|
ce:1;
|
|
#elif defined(__BIG_ENDIAN_BITFIELD)
|
|
u16 mc_bc:1,
|
|
runt:1,
|
|
mii:1,
|
|
crc:1,
|
|
res1:1,
|
|
len:11;
|
|
|
|
u16 res2:5,
|
|
len_bar:11;
|
|
|
|
u8 res3:1,
|
|
pri:3,
|
|
vlan_tag_striped:1,
|
|
vlan_ind:3;
|
|
|
|
u8 ce:1,
|
|
l3_type:2,
|
|
l4_type:3,
|
|
l3_csum_err:1,
|
|
l4_csum_err:1;
|
|
#else
|
|
#error "Please fix <asm/byteorder.h>"
|
|
#endif
|
|
|
|
} __attribute__ ((packed));
|
|
|
|
|
|
#endif /* __LINUX_USBNET_ASIX_H */
|
|
|