mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
synced 2025-12-15 19:08:54 +00:00
354 lines
8.2 KiB
C
354 lines
8.2 KiB
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include "aic_core.h"
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#include "aic_dma_id.h"
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#include "hal_dma_reg.h"
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#include "hal_dma.h"
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static struct aic_dma_dev aich_dma __ALIGNED(CACHE_LINE_SIZE) = {
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.base = DMA_BASE,
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.burst_length = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.addr_widths = AIC_DMA_BUS_WIDTH,
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};
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struct aic_dma_dev *get_aic_dma_dev(void)
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{
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return &aich_dma;
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}
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static inline s8 convert_burst(u32 maxburst)
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{
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switch (maxburst) {
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case 1:
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return 0;
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case 4:
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return 1;
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case 8:
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return 2;
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case 16:
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return 3;
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default:
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return -EINVAL;
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}
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}
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static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
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{
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switch (addr_width) {
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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return 1;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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return 2;
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case DMA_SLAVE_BUSWIDTH_8_BYTES:
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return 3;
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#ifdef AIC_DMA_DRV_V20
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case DMA_SLAVE_BUSWIDTH_16_BYTES:
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return 4;
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#endif
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default:
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/* For 1 byte width or fallback */
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return 0;
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}
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}
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int aic_set_burst(struct dma_slave_config *sconfig,
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enum dma_transfer_direction direction,
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u32 *p_cfg)
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{
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enum dma_slave_buswidth src_addr_width, dst_addr_width;
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u32 src_maxburst, dst_maxburst;
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s8 src_width, dst_width, src_burst, dst_burst;
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src_addr_width = sconfig->src_addr_width;
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dst_addr_width = sconfig->dst_addr_width;
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src_maxburst = sconfig->src_maxburst;
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dst_maxburst = sconfig->dst_maxburst;
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switch (direction) {
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case DMA_MEM_TO_DEV:
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11)
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if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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src_maxburst = src_maxburst ? src_maxburst : 8;
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#endif
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#ifdef AIC_DMA_DRV_V20
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if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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src_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES;
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src_maxburst = src_maxburst ? src_maxburst : 16;
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#endif
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break;
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case DMA_DEV_TO_MEM:
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#if defined(AIC_DMA_DRV_V10) || defined(AIC_DMA_DRV_V11)
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if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dst_maxburst = dst_maxburst ? dst_maxburst : 8;
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#endif
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#ifdef AIC_DMA_DRV_V20
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if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
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dst_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES;
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dst_maxburst = dst_maxburst ? dst_maxburst : 16;
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#endif
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break;
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default:
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return -EINVAL;
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}
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if (!(BIT(src_addr_width) & aich_dma.addr_widths))
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return -EINVAL;
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if (!(BIT(dst_addr_width) & aich_dma.addr_widths))
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return -EINVAL;
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if (!(BIT(src_maxburst) & aich_dma.burst_length))
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return -EINVAL;
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if (!(BIT(dst_maxburst) & aich_dma.burst_length))
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return -EINVAL;
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src_width = convert_buswidth(src_addr_width);
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dst_width = convert_buswidth(dst_addr_width);
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dst_burst = convert_burst(dst_maxburst);
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src_burst = convert_burst(src_maxburst);
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*p_cfg = (src_width << SRC_WIDTH_BITSHIFT) |
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(dst_width << DST_WIDTH_BITSHIFT) |
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(src_burst << SRC_BURST_BITSHIFT) |
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(dst_burst << DST_BURST_BITSHIFT);
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return 0;
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}
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struct aic_dma_task *aic_dma_task_alloc(void)
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{
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struct aic_dma_task *task;
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/* Remove the QH structure from the freelist */
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task = aich_dma.freetask;
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if (task) {
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aich_dma.freetask = task->v_next;
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memset(task, 0, sizeof(struct aic_dma_task));
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}
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return task;
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}
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static void aic_dma_task_free(struct aic_dma_task *task)
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{
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CHECK_PARAM_RET(task != NULL);
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task->v_next = aich_dma.freetask;
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aich_dma.freetask = task;
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}
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void *aic_dma_task_add(struct aic_dma_task *prev,
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struct aic_dma_task *next,
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struct aic_dma_chan *chan)
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{
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CHECK_PARAM((chan != NULL || prev != NULL) && next != NULL, NULL);
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if (!prev)
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{
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chan->desc = next;
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}
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else
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{
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prev->p_next = __pa((unsigned long)next);
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prev->v_next = next;
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}
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next->p_next = DMA_LINK_END_FLAG;
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next->v_next = NULL;
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return next;
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}
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void aic_dma_free_desc(struct aic_dma_chan *chan)
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{
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struct aic_dma_task *task;
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struct aic_dma_task *next;
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CHECK_PARAM_RET(chan != NULL);
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task = chan->desc;
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chan->desc = NULL;
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while (task)
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{
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next = task->v_next;
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aic_dma_task_free(task);
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task = next;
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}
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chan->callback = NULL;
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chan->callback_param = NULL;
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}
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enum dma_status hal_dma_chan_tx_status(struct aic_dma_chan *chan,
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u32 *left_size)
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{
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CHECK_PARAM(chan != NULL && left_size != NULL, -EINVAL);
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if (!(readl(aich_dma.base + DMA_CH_STA_REG) & BIT(chan->ch_nr)))
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return DMA_COMPLETE;
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*left_size = readl(chan->base + DMA_CH_LEFT_REG);
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return DMA_IN_PROGRESS;
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return DMA_COMPLETE;
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}
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int hal_dma_chan_stop(struct aic_dma_chan *chan)
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{
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u32 value;
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u32 irq_reg, irq_offset;
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CHECK_PARAM(chan != NULL, -EINVAL);
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irq_reg = chan->ch_nr / DMA_IRQ_CHAN_NR;
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irq_offset = chan->ch_nr % DMA_IRQ_CHAN_NR;
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/* disable irq */
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value = readl(aich_dma.base + DMA_IRQ_EN_REG(irq_reg));
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value &= ~(DMA_IRQ_MASK(irq_offset));
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writel(value, aich_dma.base + DMA_IRQ_EN_REG(irq_reg));
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/* pause */
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hal_dma_chan_pause(chan);
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/* stop */
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writel(0x00, chan->base + DMA_CH_EN_REG);
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/* resume */
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hal_dma_chan_resume(chan);
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chan->cyclic = false;
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chan->memset = false;
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/* free task list */
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aic_dma_free_desc(chan);
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return 0;
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}
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int hal_dma_chan_pause(struct aic_dma_chan *chan)
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{
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u32 val;
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CHECK_PARAM(chan != NULL, -EINVAL);
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/* pause */
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val = readl(chan->base + DMA_CH_PAUSE_REG);
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val |= DMA_CH_PAUSE;
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writel(val, chan->base + DMA_CH_PAUSE_REG);
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return 0;
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}
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int hal_dma_chan_resume(struct aic_dma_chan *chan)
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{
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u32 val;
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CHECK_PARAM(chan != NULL, -EINVAL);
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/* resume */
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val = readl(chan->base + DMA_CH_PAUSE_REG);
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val &= ~ DMA_CH_PAUSE;
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writel(DMA_CH_RESUME, chan->base + DMA_CH_PAUSE_REG);
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return 0;
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}
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int hal_dma_chan_terminate_all(struct aic_dma_chan *chan)
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{
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CHECK_PARAM(chan != NULL, -EINVAL);
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hal_dma_chan_stop(chan);
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return 0;
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}
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int hal_dma_chan_register_cb(struct aic_dma_chan *chan,
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dma_async_callback callback,
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void *callback_param)
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{
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CHECK_PARAM(chan != NULL && callback != NULL && callback_param != NULL, -EINVAL);
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chan->callback = callback;
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chan->callback_param = callback_param;
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return 0;
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}
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int hal_dma_chan_config(struct aic_dma_chan *chan,
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struct dma_slave_config *config)
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{
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CHECK_PARAM(chan != NULL && config != NULL, -EINVAL);
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memcpy(&chan->cfg, config, sizeof(*config));
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return 0;
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}
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int hal_release_dma_chan(struct aic_dma_chan *chan)
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{
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CHECK_PARAM(chan != NULL && chan->used != 0, -EINVAL);
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/* free task list */
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aic_dma_free_desc(chan);
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chan->used = 0;
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return 0;
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}
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struct aic_dma_chan *hal_request_dma_chan(void)
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{
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int i = 0;
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struct aic_dma_chan *chan;
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for (i = 0; i < AIC_DMA_CH_NUM; i++)
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{
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chan = &aich_dma.dma_chan[i];
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if (chan->used == 0)
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{
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chan->used = 1;
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chan->cyclic = false;
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chan->memset = false;
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chan->irq_type = 0;
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chan->callback = NULL;
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chan->callback_param = NULL;
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chan->desc = NULL;
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return chan;
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}
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}
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return NULL;
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}
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int hal_dma_init(void)
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{
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int i;
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aich_dma.base = DMA_BASE;
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for (i = 0; i < AIC_DMA_CH_NUM; i++) {
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aich_dma.dma_chan[i].ch_nr = i;
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aich_dma.dma_chan[i].base = aich_dma.base + 0x100
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+ i * DMA_CHAN_OFFSET;
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}
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aich_dma.freetask = NULL;
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for (i = 0; i < TASK_MAX_NUM; i++)
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aic_dma_task_free(&aich_dma.task[i]);
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for (i = 0; i < AIC_DMA_CH_NUM / DMA_IRQ_CHAN_NR; i++) {
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writel(0x0, aich_dma.base + DMA_IRQ_EN_REG(i));
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}
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return 0;
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}
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