mirror of
https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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272 lines
10 KiB
C
272 lines
10 KiB
C
/*
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* Copyright (c) 2022, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <aic_core.h>
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#include "aic_hal_clk.h"
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extern struct aic_clk_ops aic_clk_fixed_rate_ops;
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extern struct aic_clk_ops aic_clk_pll_ops;
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extern struct aic_clk_ops aic_clk_fixed_parent_ops;
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extern struct aic_clk_ops aic_clk_multi_parent_ops;
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extern struct aic_clk_ops aic_clk_disp_ops;
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/* Fixed rate clocks */
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FRCLK(CLK_OSC24M, "osc24m", CLOCK_24M);
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FRCLK(CLK_OSC32K, "osc32k", CLOCK_32K);
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/* PLL clocks */
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PLL_INT(CLK_PLL_INT0, "pll_int0", CLK_OSC24M, PARENT("osc24m"),
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PLL_INT0_GEN_REG, 0);
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PLL_INT(CLK_PLL_INT1, "pll_int1", CLK_OSC24M, PARENT("osc24m"),
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PLL_INT1_GEN_REG, 0);
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#ifdef AIC_CLK_PLL_FRA0_SSC_DIS
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PLL_FRA(CLK_PLL_FRA0, "pll_fra0", CLK_OSC24M, PARENT("osc24m"),
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PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG, PLL_FRA0_SDM_REG,
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CLK_IGNORE_UNUSED);
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#else
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PLL_SDM(CLK_PLL_FRA0, "pll_fra0", CLK_OSC24M, PARENT("osc24m"),
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PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG, PLL_FRA0_SDM_REG,
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CLK_IGNORE_UNUSED);
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#endif
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#ifdef AIC_CLK_PLL_FRA2_SSC_DIS
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PLL_FRA(CLK_PLL_FRA2, "pll_fra2", CLK_OSC24M, PARENT("osc24m"),
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PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG, PLL_FRA2_SDM_REG, 0);
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#else
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PLL_SDM(CLK_PLL_FRA2, "pll_fra2", CLK_OSC24M, PARENT("osc24m"),
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PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG, PLL_FRA2_SDM_REG, 0);
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#endif
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/* Fixed parent clocks */
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FPCLK(CLK_CPU_SRC1, "cpu_src1", CLK_PLL_INT0, PARENT("pll_int0"), CLK_CPU_REG,
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-1, -1, 0, 5);
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FPCLK(CLK_AXI_AHB_SRC1, "axi_ahb_src1", CLK_PLL_INT1, PARENT("pll_int1"),
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CLK_AXI_AHB_REG, -1, -1, 0, 5);
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FPCLK(CLK_APB0_SRC1, "apb0_src1", CLK_PLL_INT1, PARENT("pll_int1"),
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CLK_APB0_REG, -1, -1, 0, 5);
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FPCLK(CLK_APB1, "apb1", CLK_OSC24M, PARENT("osc24m"), CLK_APB1_REG, -1, -1, 0,
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0);
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FPCLK(CLK_DMA, "dma", CLK_AHB0, PARENT("ahb0"), CLK_DMA_REG, 12, -1, 0, 0);
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FPCLK(CLK_CE, "ce", CLK_PLL_INT1, PARENT("pll_int1"), CLK_CE_REG, 12, 8, 0, 5);
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FPCLK(CLK_USBD, "usb_dev", CLK_AHB0, PARENT("ahb0"), CLK_USBD_REG, 12, -1, 0,
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0);
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FPCLK(CLK_USBH0, "usb_host0", CLK_AHB0, PARENT("ahb0"), CLK_USBH0_REG, 12, -1,
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0, 0);
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FPCLK(CLK_USB_PHY0, "usb_phy0", CLK_OSC24M, PARENT("osc24m"), CLK_USB_PHY0_REG,
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-1, 8, 0, 0);
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FPCLK(CLK_GMAC0, "gmac0", CLK_PLL_INT1, PARENT("pll_int1"), CLK_GMAC0_REG, 12,
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8, 0, 5);
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FPCLK(CLK_XSPI, "xspi", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_XSPI_REG, 12, 8,
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0, 5);
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FPCLK(CLK_QSPI0, "qspi0", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_QSPI0_REG, 12,
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8, 0, 5);
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FPCLK(CLK_QSPI1, "qspi1", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_QSPI1_REG, 12,
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8, 0, 5);
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FPCLK(CLK_QSPI2, "qspi2", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_QSPI2_REG, 12,
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8, 0, 5);
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FPCLK(CLK_QSPI3, "qspi3", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_QSPI3_REG, 12,
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8, 0, 5);
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FPCLK(CLK_SDMC0, "sdmc0", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_SDMC0_REG, 12,
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8, 0, 5);
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FPCLK(CLK_SDMC1, "sdmc1", CLK_PLL_FRA0, PARENT("pll_fra0"), CLK_SDMC1_REG, 12,
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8, 0, 5);
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FPCLK(CLK_PBUS, "pbus", CLK_AHB0, PARENT("ahb0"), CLK_PBUS_REG, 12, -1, 0, 0);
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FPCLK(CLK_SYSCFG, "syscfg", CLK_OSC24M, PARENT("osc24m"), CLK_SYSCFG_REG, 12,
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-1, 0, 0);
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FPCLK(CLK_RTC, "rtc", CLK_OSC32K, PARENT("osc32k"), CLK_RTC_REG, 12, -1, 0, 0);
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FPCLK_BASE(CLK_AUDIO_SCLK, "audio_sclk", CLK_PLL_INT1, PARENT("pll_int1"), CLK_AUDIO_REG, 0,
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0, 0, 1, 49, 4);
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FPCLK(CLK_CODEC, "codec", CLK_AUDIO_SCLK, PARENT("audio_sclk"), CLK_CODEC_REG, 12,
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8, 0, 0);
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FPCLK(CLK_I2S0, "i2s0", CLK_AUDIO_SCLK, PARENT("audio_sclk"), CLK_I2S0_REG, 12, 8,
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0, 0);
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FPCLK(CLK_DE, "de", CLK_PLL_INT1, PARENT("pll_int1"), CLK_DE_REG, 12, 8, 0, 5);
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FPCLK(CLK_GE, "ge", CLK_PLL_INT1, PARENT("pll_int1"), CLK_GE_REG, 12, 8, 0, 5);
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FPCLK(CLK_VE, "ve", CLK_PLL_INT1, PARENT("pll_int1"), CLK_VE_REG, 12, 8, 0, 5);
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FPCLK(CLK_WDT, "wdt", CLK_OSC32K, PARENT("clk_32k"), CLK_WDT_REG, 12, 8, 0,
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0);
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FPCLK(CLK_SID, "sid", CLK_OSC24M, PARENT("osc24m"), CLK_SID_REG, 12, 8, 0, 0);
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FPCLK(CLK_GTC, "gtc", CLK_APB1, PARENT("apb1"), CLK_GTC_REG, 12, -1, 0, 0);
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FPCLK(CLK_GPIO, "gpio", CLK_APB0, PARENT("apb0"), CLK_GPIO_REG, 12, 8, 0, 5);
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FPCLK(CLK_UART0, "uart0", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART0_REG, 12,
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8, 0, 5);
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FPCLK(CLK_UART1, "uart1", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART1_REG, 12,
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8, 0, 5);
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FPCLK(CLK_UART2, "uart2", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART2_REG, 12,
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8, 0, 5);
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FPCLK(CLK_UART3, "uart3", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART3_REG, 12,
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8, 0, 5);
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FPCLK(CLK_UART4, "uart4", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART4_REG, 12,
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8, 0, 5);
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FPCLK(CLK_UART5, "uart5", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART5_REG, 12,
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8, 0, 5);
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FPCLK(CLK_UART6, "uart6", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART6_REG, 12,
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8, 0, 5);
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FPCLK(CLK_UART7, "uart7", CLK_PLL_INT1, PARENT("pll_int1"), CLK_UART7_REG, 12,
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8, 0, 5);
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FPCLK(CLK_I2C0, "i2c0", CLK_APB1, PARENT("apb1"), CLK_I2C0_REG, 12, -1, 0, 0);
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FPCLK(CLK_I2C1, "i2c1", CLK_APB1, PARENT("apb1"), CLK_I2C1_REG, 12, -1, 0, 0);
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FPCLK(CLK_I2C2, "i2c2", CLK_APB1, PARENT("apb1"), CLK_I2C2_REG, 12, -1, 0, 0);
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FPCLK(CLK_CAN0, "can0", CLK_APB1, PARENT("apb1"), CLK_CAN0_REG, 12, -1, 0, 0);
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FPCLK(CLK_CAN1, "can1", CLK_APB1, PARENT("apb1"), CLK_CAN1_REG, 12, -1, 0, 0);
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FPCLK(CLK_PWM, "pwm", CLK_PLL_INT1, PARENT("pll_int1"), CLK_PWM_REG, 12, 8, 0,
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5);
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FPCLK(CLK_ADCIM, "adcim", CLK_PLL_INT1, PARENT("pll_int1"), CLK_ADCIM_REG, 12,
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8, 0, 5);
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FPCLK(CLK_GPAI, "gpai", CLK_APB1, PARENT("apb1"), CLK_GPAI_REG, 12, -1, 0, 0);
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FPCLK(CLK_RTP, "rtp", CLK_APB1, PARENT("apb1"), CLK_RTP_REG, 12, -1, 0, 0);
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FPCLK(CLK_TSEN, "tsen", CLK_APB1, PARENT("apb1"), CLK_TSEN_REG, 12, -1, 0, 0);
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FPCLK(CLK_CIR, "cir", CLK_APB1, PARENT("apb1"), CLK_CIR_REG, 12, -1, 0, 0);
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FPCLK(CLK_DVP, "dvp", CLK_PLL_INT1, PARENT("pll_int1"), CLK_DVP_REG, 12, 8, 0,
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5);
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FPCLK(CLK_MTOP, "mtop", CLK_APB0, PARENT("apb0"), CLK_MTOP_REG, 12, -1, 0, 0);
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FPCLK(CLK_SPIENC, "spienc", CLK_AHB0, PARENT("ahb0"), CLK_SPIENC_REG, 12, 8, 0,
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0);
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FPCLK(CLK_RGB, "rgb", CLK_SCLK, PARENT("sclk"), CLK_RGB_REG, 12, 8, 0, 0);
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FPCLK(CLK_LVDS, "lvds", CLK_SCLK, PARENT("sclk"), CLK_LVDS_REG, 12, 8, 0, 0);
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FPCLK(CLK_MIPIDSI, "mipidsi", CLK_SCLK, PARENT("sclk"), CLK_MIPID_REG, 12, 8, 0,
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0);
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FPCLK(CLK_PSADC, "psadc", CLK_PLL_INT1, PARENT("pll_int1"), CLK_PSADC_REG, 12, 8, 0, 5);
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FPCLK(CLK_PWMCS, "pwmcs", CLK_PLL_INT1, PARENT("pll_int1"), CLK_PWMCS_REG, 12, 8, 0, 0);
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FPCLK(CLK_PWMCS_SDFM, "pwmcs_sdfm", CLK_PLL_INT1, PARENT("pll_int1"),
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CLK_PWMCS_SDFM_REG, -1, -1, 0, 5);
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/* Multi parent clocks */
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static const u8 axi_ahb_src_sels[] = {
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/* "osc24m", "ahb0_src1", */
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CLK_OSC24M,
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CLK_AXI_AHB_SRC1,
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};
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static const u8 apb0_src_sels[] = {
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/* "osc24m",
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"apb0_src1", */
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CLK_OSC24M,
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CLK_APB0_SRC1,
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};
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static const u8 cpu_src_sels[] = {
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/* "osc24m",
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"cpu_src1", */
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CLK_OSC24M,
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CLK_CPU_SRC1,
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};
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static const u8 outclk_src_sels[] = {
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/* "pll_int1",
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"pll_fra1",
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"pll_fra2", */
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CLK_PLL_INT1,
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0,
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CLK_PLL_FRA2,
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};
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MPCLK(CLK_CPU, "cpu", cpu_src_sels, CLK_CPU_REG, -1, 8, 1, 0, 0);
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MPCLK(CLK_AXI0, "axi0", axi_ahb_src_sels, CLK_AXI_AHB_REG, -1, 8, 1, 0, 0);
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MPCLK(CLK_AHB0, "ahb0", axi_ahb_src_sels, CLK_AXI_AHB_REG, -1, 8, 1, 0, 0);
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MPCLK(CLK_APB0, "apb0", apb0_src_sels, CLK_APB0_REG, -1, 8, 1, 0, 0);
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MPCLK(CLK_OUT0, "clk_out0", outclk_src_sels, CLK_OUT0_REG, 16, 12, 3, 0, 8);
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MPCLK(CLK_OUT1, "clk_out1", outclk_src_sels, CLK_OUT1_REG, 16, 12, 3, 0, 8);
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MPCLK(CLK_OUT2, "clk_out2", outclk_src_sels, CLK_OUT2_REG, 16, 12, 3, 0, 8);
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MPCLK(CLK_OUT3, "clk_out3", outclk_src_sels, CLK_OUT3_REG, 16, 12, 3, 0, 8);
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/* Disp clocks */
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DISPCLK(CLK_PIX, "pixclk", CLK_SCLK, PARENT("sclk"), CLK_DISP_REG, 0, 0, 4, 5,
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10, 2, 12, 2);
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DISPCLK(CLK_SCLK, "sclk", CLK_PLL_FRA2, PARENT("pll_fra2"), CLK_DISP_REG, 0, 3,
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0, 0, 0, 0, 0, 0);
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/* Clock cfg array */
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const struct aic_clk_comm_cfg *aic_clk_cfgs[AIC_CLK_END] = {
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/* Fixed rate clock */
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DUMMY_CFG(CLK_DUMMY),
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AIC_CLK_CFG(CLK_OSC24M),
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AIC_CLK_CFG(CLK_OSC32K),
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/* PLL clock */
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AIC_CLK_CFG(CLK_PLL_INT0),
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AIC_CLK_CFG(CLK_PLL_INT1),
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AIC_CLK_CFG(CLK_PLL_FRA0),
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AIC_CLK_CFG(CLK_PLL_FRA2),
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/* fixed factor clock */
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AIC_CLK_CFG(CLK_AXI_AHB_SRC1),
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AIC_CLK_CFG(CLK_APB0_SRC1),
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AIC_CLK_CFG(CLK_CPU_SRC1),
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/* system clock */
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AIC_CLK_CFG(CLK_AXI0),
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AIC_CLK_CFG(CLK_AHB0),
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AIC_CLK_CFG(CLK_APB0),
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AIC_CLK_CFG(CLK_APB1),
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AIC_CLK_CFG(CLK_CPU),
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/* Peripheral clock */
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AIC_CLK_CFG(CLK_DMA),
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AIC_CLK_CFG(CLK_CE),
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AIC_CLK_CFG(CLK_USBD),
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AIC_CLK_CFG(CLK_USBH0),
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AIC_CLK_CFG(CLK_USB_PHY0),
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AIC_CLK_CFG(CLK_GMAC0),
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AIC_CLK_CFG(CLK_XSPI),
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AIC_CLK_CFG(CLK_QSPI0),
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AIC_CLK_CFG(CLK_QSPI1),
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AIC_CLK_CFG(CLK_QSPI2),
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AIC_CLK_CFG(CLK_QSPI3),
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AIC_CLK_CFG(CLK_SDMC0),
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AIC_CLK_CFG(CLK_SDMC1),
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AIC_CLK_CFG(CLK_SYSCFG),
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AIC_CLK_CFG(CLK_RTC),
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AIC_CLK_CFG(CLK_SPIENC),
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AIC_CLK_CFG(CLK_I2S0),
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AIC_CLK_CFG(CLK_AUDIO_SCLK),
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AIC_CLK_CFG(CLK_CODEC),
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AIC_CLK_CFG(CLK_RGB),
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AIC_CLK_CFG(CLK_LVDS),
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AIC_CLK_CFG(CLK_MIPIDSI),
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AIC_CLK_CFG(CLK_DE),
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AIC_CLK_CFG(CLK_GE),
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AIC_CLK_CFG(CLK_VE),
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AIC_CLK_CFG(CLK_WDT),
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AIC_CLK_CFG(CLK_SID),
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AIC_CLK_CFG(CLK_GTC),
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AIC_CLK_CFG(CLK_GPIO),
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AIC_CLK_CFG(CLK_UART0),
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AIC_CLK_CFG(CLK_UART1),
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AIC_CLK_CFG(CLK_UART2),
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AIC_CLK_CFG(CLK_UART3),
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AIC_CLK_CFG(CLK_UART4),
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AIC_CLK_CFG(CLK_UART5),
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AIC_CLK_CFG(CLK_UART6),
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AIC_CLK_CFG(CLK_UART7),
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AIC_CLK_CFG(CLK_I2C0),
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AIC_CLK_CFG(CLK_I2C1),
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AIC_CLK_CFG(CLK_I2C2),
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AIC_CLK_CFG(CLK_CAN0),
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AIC_CLK_CFG(CLK_CAN1),
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AIC_CLK_CFG(CLK_PWM),
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AIC_CLK_CFG(CLK_ADCIM),
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AIC_CLK_CFG(CLK_GPAI),
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AIC_CLK_CFG(CLK_RTP),
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AIC_CLK_CFG(CLK_TSEN),
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AIC_CLK_CFG(CLK_CIR),
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AIC_CLK_CFG(CLK_DVP),
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AIC_CLK_CFG(CLK_PBUS),
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AIC_CLK_CFG(CLK_MTOP),
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AIC_CLK_CFG(CLK_PSADC),
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AIC_CLK_CFG(CLK_PWMCS),
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AIC_CLK_CFG(CLK_PWMCS_SDFM),
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/* Display clock */
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AIC_CLK_CFG(CLK_PIX),
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AIC_CLK_CFG(CLK_SCLK),
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/* Output clock */
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AIC_CLK_CFG(CLK_OUT0),
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AIC_CLK_CFG(CLK_OUT1),
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AIC_CLK_CFG(CLK_OUT2),
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AIC_CLK_CFG(CLK_OUT3),
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};
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