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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/*
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* Copyright (c) 2022, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARTINCHIP_HAL_DMA_REG_H_
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#define _ARTINCHIP_HAL_DMA_REG_H_
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#include "aic_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define TASK_MAX_NUM 24
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#define DELAY_DEF_VAL 0x40
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/*
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* define dma register list
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*/
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#define DMA_IRQ_EN_REG (0x0000)
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#define DMA_IRQ_STA_REG (0x0010)
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#define DMA_GATE_REG (0x0028)
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#define DMA_CH_STA_REG (0x0030)
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#define DMA_CH_EN_REG (0x0000)
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#define DMA_CH_PAUSE_REG (0x0004)
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#define DMA_CH_TASK_REG (0x0008)
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#define DMA_CH_CFG_REG (0x000C)
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#define DMA_CH_SRC_REG (0x0010)
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#define DMA_CH_SINK_REG (0x0014)
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#define DMA_CH_LEFT_REG (0x0018)
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#define DMA_CH_MODE_REG (0x0028)
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#define DMA_CH_PKG_NUM_REG (0x0030)
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#define DMA_CH_MEMSET_VAL_REG (0x0034)
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/*
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* define macro for access register for specific channel
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*/
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#define DMA_IRQ_HALF_TASK BIT(0)
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#define DMA_IRQ_ONE_TASK BIT(1)
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#define DMA_IRQ_ALL_TASK BIT(2)
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#define DMA_IRQ_CH_WIDTH (4)
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#define DMA_IRQ_SHIFT(ch) (DMA_IRQ_CH_WIDTH * (ch))
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#define DMA_IRQ_MASK(ch) (GENMASK(2, 0) << DMA_IRQ_SHIFT(ch))
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#define AIC_DMA_BUS_WIDTH \
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(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
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/*
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* define bit index in channel configuration register
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*/
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#define DST_WIDTH_BITSHIFT 25
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#define DST_ADDR_BITSHIFT 24
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#define DST_BURST_BITSHIFT 22
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#define DST_PORT_BITSHIFT 16
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#define SRC_WIDTH_BITSHIFT 9
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#define SRC_ADDR_BITSHIFT 8
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#define SRC_BURST_BITSHIFT 6
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#define SRC_PORT_BITSHIFT 0
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#define ADDR_LINEAR_MODE 0
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#define ADDR_FIXED_MODE 1
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#define DMA_WAIT_MODE 0
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#define DMA_HANDSHAKE_MODE 1
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#define DMA_DST_MODE_SHIFT 3
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#define DMA_SRC_MODE_SHIFT 2
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#define DMA_S_WAIT_D_HANDSHAKE (DMA_HANDSHAKE_MODE << DMA_DST_MODE_SHIFT)
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#define DMA_S_HANDSHAKE_D_WAIT (DMA_HANDSHAKE_MODE << DMA_SRC_MODE_SHIFT)
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#define DMA_S_WAIT_D_WAIT (DMA_WAIT_MODE)
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#define DMA_DRQ_PORT_MASK 0x3F
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#define DMA_LINK_END_FLAG 0xfffff800
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/*
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* define bit index in channel pause register
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*/
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#define DMA_CH_PAUSE 0x1
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#define DMA_CH_MEMSET 0x10
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#define DMA_CH_BYTEMODE 0x20
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#ifdef __cplusplus
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}
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#endif
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#endif /*_ARTINCHIP_HAL_DMA_REG_H_ */
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