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393 lines
11 KiB
C
393 lines
11 KiB
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#include "aic_core.h"
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#include "hal_gpai.h"
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#include "aic_hal_clk.h"
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/* Register definition of GPAI Controller */
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#define GPAI_MCR 0x000
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#define GPAI_INTR 0x004
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#define GPAI_CHnCR(n) (0x100 + (((n) & 0x7) << 6) + 0x00)
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#define GPAI_CHnINT(n) (0x100 + (((n) & 0x7) << 6) + 0x04)
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#define GPAI_CHnPSI(n) (0x100 + (((n) & 0x7) << 6) + 0x08)
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#define GPAI_CHnHLAT(n) (0x100 + (((n) & 0x7) << 6) + 0x10)
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#define GPAI_CHnLLAT(n) (0x100 + (((n) & 0x7) << 6) + 0x14)
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#define GPAI_CHnACR(n) (0x100 + (((n) & 0x7) << 6) + 0x18)
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#define GPAI_CHnFCR(n) (0x100 + (((n) & 0x7) << 6) + 0x20)
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#define GPAI_CHnDATA(n) (0x100 + (((n) & 0x7) << 6) + 0x24)
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#define GPAI_VERSION 0xFFC
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#define GPAI_MCR_CH0_EN BIT(8)
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#define GPAI_MCR_CH_EN(n) (GPAI_MCR_CH0_EN << (n))
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#define GPAI_MCR_EN BIT(0)
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#define GPAI_INTR_CH0_INT_FLAG BIT(16)
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#define GPAI_INTR_CH_INT_FLAG(n) (GPAI_INTR_CH0_INT_FLAG << (n))
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#define GPAI_INTR_CH0_INT_EN BIT(0)
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#define GPAI_INTR_CH_INT_EN(n) (GPAI_INTR_CH0_INT_EN << (n))
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#define GPAI_CHnCR_SBC_SHIFT 24
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#define GPAI_CHnCR_SBC_2_POINTS 1
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#define GPAI_CHnCR_SBC_4_POINTS 2
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#define GPAI_CHnCR_SBC_8_POINTS 3
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#define GPAI_CHnCR_SBC_SHIFT 24
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#define GPAI_CHnCR_SBC_MASK GENMASK(25, 24)
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#define GPAI_CHnCR_HIGH_ADC_PRIORITY BIT(4)
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#define GPAI_CHnCR_PERIOD_SAMPLE_EN BIT(1)
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#define GPAI_CHnCR_SINGLE_SAMPLE_EN BIT(0)
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#define GPAI_CHnINT_LLA_RM_FLAG BIT(23)
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#define GPAI_CHnINT_LLA_VALID_FLAG BIT(22)
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#define GPAI_CHnINT_HLA_RM_FLAG BIT(21)
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#define GPAI_CHnINT_HLA_VALID_FLAG BIT(20)
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#define GPAI_CHnINT_FIFO_ERR_FLAG BIT(17)
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#define GPAI_CHnINT_DRDY_FLG BIT(16)
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#define GPAI_CHnINT_LLA_RM_IE BIT(7)
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#define GPAI_CHnINT_LLA_VALID_IE BIT(6)
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#define GPAI_CHnINT_HLA_RM_IE BIT(5)
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#define GPAI_CHnINT_HLA_VALID_IE BIT(4)
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#define GPAI_CHnINT_FIFO_ERR_IE BIT(1)
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#define GPAI_CHnINT_DAT_RDY_IE BIT(0)
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#define GPAI_CHnLAT_HLLA_RM_THD_SHIFT 16
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#define GPAI_CHnLAT_HLLA_RM_THD_MASK GENMASK(27, 16)
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#define GPAI_CHnLAT_HLLA_THD_MASK GENMASK(11, 0)
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#define GPAI_CHnLAT_HLA_RM_THD(n) ((n) - 30)
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#define GPAI_CHnLAT_LLA_RM_THD(n) ((n) + 30)
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#define GPAI_CHnACR_DISCARD_NOR_DAT BIT(6)
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#define GPAI_CHnACR_DISCARD_LL_DAT BIT(5)
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#define GPAI_CHnACR_DISCARD_HL_DAT BIT(4)
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#define GPAI_CHnACR_LLA_EN BIT(1)
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#define GPAI_CHnACR_HLA_EN BIT(0)
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#define GPAI_CHnFCR_DAT_CNT_MAX(ch) ((ch) > 1 ? 0x8 : 0x40)
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#define GPAI_CHnFCR_DAT_CNT_SHIFT 24
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#define GPAI_CHnFCR_DAT_CNT_MASK GENMASK(30, 24)
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#define GPAI_CHnFCR_UF_STS BIT(18)
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#define GPAI_CHnFCR_OF_STS BIT(17)
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#define GPAI_CHnFCR_DAT_RDY_THD_SHIFT 8
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#define GPAI_CHnFCR_DAT_RDY_THD_MASK GENMASK(15, 8)
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#define GPAI_CHnFCR_FLUSH BIT(0)
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// TODO: irq_handle() should get 'struct aic_gpai_ch *' from 'void *arg'
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extern struct aic_gpai_ch aic_gpai_chs[];
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static u32 aic_gpai_ch_num = 0; // the number of available channel
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static inline void gpai_writel(u32 val, int reg)
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{
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writel(val, GPAI_BASE + reg);
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}
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static inline u32 gpai_readl(int reg)
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{
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return readl(GPAI_BASE + reg);
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}
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// TODO: Add the transform algorithm, offered by SD later
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static s32 gpai_data2vol(u16 data)
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{
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return data;
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}
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static u16 gpai_vol2data(s32 vol)
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{
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return vol;
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}
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static u32 gpai_ms2itv(u32 pclk_rate, u32 ms)
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{
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u32 tmp = 0;
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tmp = pclk_rate / 1000;
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tmp *= ms;
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return tmp;
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}
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static void gpai_reg_enable(int offset, int bit, int enable)
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{
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int tmp = gpai_readl(offset);
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if (enable)
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tmp |= bit;
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else
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tmp &= ~bit;
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gpai_writel(tmp, offset);
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}
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void aich_gpai_enable(int enable)
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{
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gpai_reg_enable(GPAI_MCR, GPAI_MCR_EN, enable);
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}
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void aich_gpai_ch_enable(u32 ch, int enable)
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{
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gpai_reg_enable(GPAI_MCR, GPAI_MCR_CH_EN(ch), enable);
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}
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static void gpai_int_enable(u32 ch, u32 enable, u32 detail)
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{
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u32 val = 0;
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val = gpai_readl(GPAI_INTR);
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if (enable) {
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val |= GPAI_INTR_CH_INT_EN(ch);
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gpai_writel(detail, GPAI_CHnINT(ch));
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} else {
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val &= ~GPAI_INTR_CH_INT_EN(ch);
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gpai_writel(0, GPAI_CHnINT(ch));
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}
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gpai_writel(val, GPAI_INTR);
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}
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static void gpai_fifo_init(u32 ch)
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{
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u32 val = 0;
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val = 1 << GPAI_CHnFCR_DAT_RDY_THD_SHIFT;
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gpai_writel(val, GPAI_CHnFCR(ch));
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}
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static void gpai_fifo_flush(u32 ch)
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{
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u32 val = gpai_readl(GPAI_CHnFCR(ch));
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if (val & GPAI_CHnFCR_UF_STS)
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pr_err("ch%d FIFO is Underflow!%#x\n", ch, val);
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if (val & GPAI_CHnFCR_OF_STS)
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pr_err("ch%d FIFO is Overflow!%#x\n", ch, val);
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gpai_writel(val | GPAI_CHnFCR_FLUSH, GPAI_CHnFCR(ch));
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}
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static void gpai_single_mode(u32 ch)
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{
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u32 val = 0;
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val = gpai_readl(GPAI_CHnCR(ch));
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val |= GPAI_CHnCR_SBC_8_POINTS << GPAI_CHnCR_SBC_SHIFT
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| GPAI_CHnCR_SINGLE_SAMPLE_EN;
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gpai_writel(val, GPAI_CHnCR(ch));
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gpai_int_enable(ch, 1,
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GPAI_CHnINT_DAT_RDY_IE | GPAI_CHnINT_FIFO_ERR_IE);
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}
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/* Only in period mode, HLA and LLA are available */
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static void gpai_period_mode(struct aic_gpai_ch *chan, u32 pclk)
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{
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u32 val, acr = 0, ch = chan->id;
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u32 detail = GPAI_CHnINT_DAT_RDY_IE | GPAI_CHnINT_FIFO_ERR_IE;
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if (chan->hla_enable) {
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detail |= GPAI_CHnINT_HLA_RM_IE | GPAI_CHnINT_HLA_VALID_IE;
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val = ((gpai_vol2data(chan->hla_rm_thd) << GPAI_CHnLAT_HLLA_RM_THD_SHIFT)
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& GPAI_CHnLAT_HLLA_RM_THD_MASK)
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| (gpai_vol2data(chan->hla_thd) & GPAI_CHnLAT_HLLA_THD_MASK);
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gpai_writel(val, GPAI_CHnHLAT(ch));
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acr |= GPAI_CHnACR_HLA_EN;
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}
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if (chan->lla_enable) {
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detail |= GPAI_CHnINT_LLA_VALID_IE | GPAI_CHnINT_LLA_RM_IE;
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val = ((gpai_vol2data(chan->lla_rm_thd) << GPAI_CHnLAT_HLLA_RM_THD_SHIFT)
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& GPAI_CHnLAT_HLLA_RM_THD_MASK)
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| (gpai_vol2data(chan->lla_thd) & GPAI_CHnLAT_HLLA_THD_MASK);
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gpai_writel(val, GPAI_CHnLLAT(ch));
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acr |= GPAI_CHnACR_LLA_EN;
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}
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gpai_int_enable(ch, 1, detail);
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gpai_writel(acr, GPAI_CHnACR(ch));
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val = gpai_ms2itv(pclk, chan->smp_period);
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gpai_writel(val, GPAI_CHnPSI(ch));
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val = gpai_readl(GPAI_CHnCR(ch));
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val |= GPAI_CHnCR_SBC_8_POINTS << GPAI_CHnCR_SBC_SHIFT
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| GPAI_CHnCR_PERIOD_SAMPLE_EN;
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gpai_writel(val, GPAI_CHnCR(ch));
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}
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int aich_gpai_ch_init(struct aic_gpai_ch *chan, u32 pclk)
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{
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aich_gpai_ch_enable(chan->id, 1);
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gpai_fifo_init(chan->id);
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if (chan->mode == AIC_GPAI_MODE_PERIOD)
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gpai_period_mode(chan, pclk);
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/* For single mode, should init the channel in .read() */
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return 0;
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}
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int aich_gpai_read(struct aic_gpai_ch *chan, u32 *val, u32 timeout)
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{
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int ret = 0;
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u32 ch = chan->id;
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if (!chan->available) {
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hal_log_err("Ch%d is unavailable!\n", chan->id);
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return -ENODATA;
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}
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#ifndef CONFIG_ARTINCHIP_ADCIM_DM
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if (chan->mode == AIC_GPAI_MODE_PERIOD) {
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*val = gpai_data2vol(chan->latest_data);
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return 0;
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}
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#endif
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aich_gpai_ch_enable(ch, 1);
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gpai_single_mode(ch);
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ret = aicos_sem_take(chan->complete, timeout);
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if (ret < 0) {
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hal_log_err("Ch%d read timeout!\n", ch);
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aich_gpai_ch_enable(ch, 0);
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return -ETIMEDOUT;
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}
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// aich_gpai_ch_enable(ch, 0);
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if (val)
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*val = gpai_data2vol(chan->latest_data);
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return 0;
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}
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void aich_gpai_status_show(struct aic_gpai_ch *chan)
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{
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int mcr = gpai_readl(GPAI_MCR);
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int version = gpai_readl(GPAI_VERSION);
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printf("In GPAI V%d.%02d:\n"
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"Ch Mode Enable Value LTA HTA\n"
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"%2d %4s %6d %5d %4d %4d\n",
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version >> 8, version & 0xff,
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chan->id, chan->mode ? "P" : "S",
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mcr & GPAI_MCR_CH_EN(chan->id) ? 1 : 0,
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chan->latest_data, chan->lla_thd, chan->hla_thd);
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}
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static int aic_gpai_read_ch(struct aic_gpai_ch *chan)
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{
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u32 i, ch = chan->id;
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u32 cnt = (gpai_readl(GPAI_CHnFCR(ch)) & GPAI_CHnFCR_DAT_CNT_MASK)
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>> GPAI_CHnFCR_DAT_CNT_SHIFT;
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if (unlikely(cnt == 0 || cnt > GPAI_CHnFCR_DAT_CNT_MAX(ch))) {
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pr_err("ch%d invalid data count %d\n", ch, cnt);
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return -1;
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}
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/* Just record the last data as to now */
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for (i = 0; i < cnt; i++) {
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chan->latest_data = gpai_readl(GPAI_CHnDATA(ch));
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// pr_debug("ch%d data%d %d\n", ch, i, chan->latest_data);
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}
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pr_debug("There are %d data ready in ch%d, last %d\n", cnt,
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ch, chan->latest_data);
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return 0;
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}
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struct aic_gpai_ch *hal_gpai_ch_is_valid(u32 ch)
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{
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s32 i;
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if (ch >= AIC_GPAI_CH_NUM) {
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pr_err("Invalid channel %d\n", ch);
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return NULL;
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}
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for (i = 0; i < aic_gpai_ch_num; i++) {
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if (aic_gpai_chs[i].id != ch)
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continue;
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if (aic_gpai_chs[i].available)
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return &aic_gpai_chs[i];
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else
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break;
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}
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pr_warn("Ch%d is unavailable!\n", ch);
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return NULL;
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}
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irqreturn_t aich_gpai_isr(int irq, void *arg)
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{
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u32 ch_flag = 0, ch_int = 0;
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int i;
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struct aic_gpai_ch *chan = NULL;
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ch_flag = gpai_readl(GPAI_INTR);
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for (i = 0; i < AIC_GPAI_CH_NUM; i++) {
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if (!(ch_flag & GPAI_INTR_CH_INT_FLAG(i)))
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continue;
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chan = hal_gpai_ch_is_valid(i);
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if (!chan)
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return IRQ_NONE;
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ch_int = gpai_readl(GPAI_CHnINT(i));
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gpai_writel(ch_int, GPAI_CHnINT(i));
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if (ch_int & GPAI_CHnINT_DRDY_FLG) {
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aic_gpai_read_ch(chan);
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if (chan->mode == AIC_GPAI_MODE_SINGLE)
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aicos_sem_give(chan->complete);
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}
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if (ch_int & GPAI_CHnINT_LLA_VALID_FLAG)
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pr_warn("LLA: ch%d %d!\n", i, chan->latest_data);
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if (ch_int & GPAI_CHnINT_LLA_RM_FLAG)
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pr_warn("LLA removed: ch%d %d\n", i,
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chan->latest_data);
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if (ch_int & GPAI_CHnINT_HLA_VALID_FLAG)
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pr_warn("HLA: ch%d %d!\n", i, chan->latest_data);
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if (ch_int & GPAI_CHnINT_HLA_RM_FLAG)
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pr_warn("HLA removed: ch%d %d\n", i,
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chan->latest_data);
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if (ch_int & GPAI_CHnINT_FIFO_ERR_FLAG)
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gpai_fifo_flush(i);
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}
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pr_debug("IRQ flag %#x, detail %#x\n", ch_flag, ch_int);
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return IRQ_HANDLED;
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}
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s32 hal_gpai_clk_init(void)
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{
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s32 ret = 0;
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ret = hal_clk_enable(CLK_GPAI);
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if (ret < 0) {
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pr_err("GPAI clk enable failed!");
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return -1;
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}
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ret = hal_clk_enable_deassertrst(CLK_GPAI);
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if (ret < 0) {
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pr_err("GPAI reset deassert failed!");
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return -1;
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}
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return ret;
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}
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void hal_gpai_clk_get(struct aic_gpai_ch *chan)
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{
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chan->pclk_rate = hal_clk_get_freq(hal_clk_get_parent(CLK_GPAI));
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}
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void hal_gpai_set_ch_num(u32 num)
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{
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aic_gpai_ch_num = num;
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}
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