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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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425 lines
12 KiB
C
425 lines
12 KiB
C
/*
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* Copyright (c) 2022-2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: geo <guojun.dong@artinchip.com>
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*/
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#include <rtconfig.h>
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#include <stdbool.h>
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#include <string.h>
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#include <hal_i2c.h>
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#include "aic_errno.h"
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#define gen_reg(val) (volatile void *)(val)
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#define USEC_PER_SEC (1000000)
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int aic_i2c_init(uint32_t i2c_idx)
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{
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int ret = 0;
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ret = hal_clk_enable_deassertrst(CLK_I2C0 + i2c_idx);
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if (ret < 0)
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pr_err("I2C clock and reset init error\n");
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return ret;
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}
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void hal_i2c_set_hold(ptr_t reg_base, u32 val)
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{
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writel(val, reg_base + I2C_SDA_HOLD);
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}
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int aic_i2c_set_master_slave_mode(unsigned long reg_base, uint8_t mode)
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{
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uint32_t reg_val;
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CHECK_PARAM(reg_base, -EINVAL);
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reg_val = readl(gen_reg(reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_MASTER_SLAVE_SELECT_MASK;
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if (mode)
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reg_val |= I2C_ENABLE_MASTER_DISABLE_SLAVE;
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else
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/* slave mode, and will detect stop signal only if addressed */
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reg_val |= I2C_CTL_STOP_DET_IFADDR;
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writel(reg_val, gen_reg(reg_base + I2C_CTL));
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return 0;
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}
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int aic_i2c_master_10bit_addr(unsigned long reg_base, uint8_t enable)
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{
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uint32_t reg_val;
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CHECK_PARAM(reg_base, -EINVAL);
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reg_val = readl(gen_reg(reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_10BIT_SELECT_MASTER;
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if (enable)
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reg_val |= I2C_CTL_10BIT_SELECT_MASTER;
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writel(reg_val, gen_reg(reg_base + I2C_CTL));
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return 0;
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}
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int aic_i2c_slave_10bit_addr(unsigned long reg_base, uint8_t enable)
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{
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uint32_t reg_val;
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CHECK_PARAM(reg_base, -EINVAL);
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reg_val = readl(gen_reg(reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_10BIT_SELECT_SLAVE;
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if (enable)
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reg_val |= I2C_CTL_10BIT_SELECT_SLAVE;
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writel(reg_val, gen_reg(reg_base + I2C_CTL));
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return 0;
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}
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static int i2c_scl_cnt(uint32_t clk_freq, uint8_t isStandardSpeed,
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uint16_t *hcnt, uint16_t *lcnt)
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{
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uint16_t hcnt_tmp, lcnt_tmp;
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CHECK_PARAM(hcnt, -EINVAL);
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CHECK_PARAM(lcnt, -EINVAL);
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if (isStandardSpeed) {
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/* Minimum value of tHIGH in standard mode is 4000ns
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* Plus 2 is just to increase the time of tHIGH, appropriately.
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* SS_MIN_SCL_HIGH * (clk_freq / 1000) is just to prevent 32bits
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* overflow. SS_MIN_SCL_HIGH * clk_freq will 32bits overflow.
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*/
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hcnt_tmp = SS_MIN_SCL_HIGH * (clk_freq / 1000) / 1000000 + 2;
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lcnt_tmp = SS_MIN_SCL_LOW * (clk_freq / 1000) / 1000000 + 2;
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} else {
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/* If isStandardSpeed is false, set i2c to fast speed
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* Minimum value of tHIGH in fast mode is 600ns
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* Plus 3 is just to increase the time of tHIGH, appropriately.
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* FS_MIN_SCL_HIGH * (clk_freq / 1000)
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*/
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hcnt_tmp = FS_MIN_SCL_HIGH * (clk_freq / 1000) / 1000000 + 2;
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lcnt_tmp = FS_MIN_SCL_LOW * (clk_freq / 1000) / 1000000 + 2;
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}
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*hcnt = hcnt_tmp;
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*lcnt = lcnt_tmp;
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return 0;
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}
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int aic_i2c_speed_mode_select(unsigned long reg_base, uint32_t clk_freq,
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uint8_t mode)
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{
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uint32_t reg_val;
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uint16_t hcnt, lcnt;
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int ret;
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CHECK_PARAM(reg_base, -EINVAL);
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reg_val = readl(gen_reg(reg_base + I2C_CTL));
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reg_val &= ~I2C_CTL_SPEED_MODE_SELECT_MASK;
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if (mode) {
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reg_val |= I2C_CTL_SPEED_MODE_FS;
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/* Calculate fast speed HCNT and LCNT */
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ret = i2c_scl_cnt(clk_freq, false, &hcnt, &lcnt);
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if (ret)
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return ret;
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writel(hcnt, gen_reg(reg_base + I2C_FS_SCL_HCNT));
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writel(lcnt, gen_reg(reg_base + I2C_FS_SCL_LCNT));
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} else {
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reg_val |= I2C_CTL_SPEED_MODE_SS;
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/* Calculate standard speed HCNT and LCNT */
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ret = i2c_scl_cnt(clk_freq, true, &hcnt, &lcnt);
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if (ret)
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return ret;
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writel(hcnt, gen_reg(reg_base + I2C_SS_SCL_HCNT));
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writel(lcnt, gen_reg(reg_base + I2C_SS_SCL_LCNT));
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}
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writel(reg_val, gen_reg(reg_base + I2C_CTL));
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return 0;
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}
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/*
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* Set the target address when i2c worked as master mode
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*/
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void aic_i2c_target_addr(unsigned long reg_base, uint32_t addr)
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{
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uint32_t reg_val;
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reg_val = readl(gen_reg(reg_base + I2C_TAR));
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reg_val &= ~I2C_TAR_ADDR_MASK;
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reg_val |= addr;
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writel(reg_val, gen_reg(reg_base + I2C_TAR));
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}
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int aic_i2c_slave_own_addr(unsigned long reg_base, uint32_t addr)
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{
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CHECK_PARAM(reg_base, -EINVAL);
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CHECK_PARAM(!(addr > I2C_TAR_ADDR_MASK), -EINVAL);
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writel(addr, gen_reg(reg_base + I2C_SAR));
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return 0;
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}
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/**
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\brief Start sending data as IIC Master.
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This function is non-blocking,\ref csi_iic_event_e is signaled when transfer completes or error happens.
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\param[in] iic handle to operate.
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\param[in] devaddr iic addrress of slave device. |_BIT[7:1]devaddr_|_BIT[0]R/W_|
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eg: BIT[7:0] = 0xA0, devaddr = 0x50.
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\param[in] data data to send to IIC Slave
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\param[in] num size of data items to send
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\return \ref csi_error_t
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*/
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int aic_i2c_master_send_msg_async(unsigned long reg_base, uint32_t devaddr,
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const void *data, uint32_t size)
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{
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// CSI_PARAM_CHK(iic, CSI_ERROR);
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// CSI_PARAM_CHK(data, CSI_ERROR);
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// CSI_PARAM_CHK(size, CSI_ERROR);
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int ret = EOK;
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// csi_irq_attach((uint32_t)iic->dev.irq_num, &aich_twi_master_tx_handler, &iic->dev);
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// csi_irq_enable((uint32_t)iic->dev.irq_num);
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// iic_master_send_intr(iic, devaddr, data, size);
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return ret;
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}
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/**
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\brief wait_iic_transmit
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\param[in] reg_base: i2c
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\return \ref csi_error_t
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*/
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static int32_t aic_i2c_wait_iic_transmit(unsigned long reg_base,
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uint32_t timeout)
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{
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int32_t ret = I2C_OK;
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do {
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uint32_t timecount = timeout + rt_tick_get();
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while ((aic_i2c_get_transmit_fifo_num(reg_base) != 0U) &&
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(ret == EOK)) {
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if (rt_tick_get() >= timecount) {
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ret = I2C_TIMEOUT;
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}
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}
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} while (0);
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return ret;
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}
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/**
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\brief wait_iic_receive
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\param[in] iic handle of iic instance
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\param[in] wait receive data num
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\return \ref csi_error_t
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*/
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static int32_t aic_i2c_wait_receive(unsigned long reg_base,
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uint32_t wait_data_num, uint32_t timeout)
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{
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int32_t ret = I2C_OK;
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do {
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uint32_t timecount = timeout + rt_tick_get();
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while ((aic_i2c_get_receive_fifo_num(reg_base) < wait_data_num) &&
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(ret == I2C_OK)) {
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if (rt_tick_get() >= timecount) {
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ret = I2C_TIMEOUT;
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}
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}
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} while (0);
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return ret;
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}
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/**
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\brief aic_i2c_master_send_msg
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\param[in] reg_base
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\param[in]
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\return bytes of sent msg
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*/
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int32_t aic_i2c_master_send_msg(unsigned long reg_base, struct rt_i2c_msg *msg)
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{
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CHECK_PARAM(msg, -EINVAL);
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int32_t ret = I2C_OK;
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uint16_t size = msg->len;
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uint32_t send_count = 0;
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uint32_t stop_time = 0;
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uint32_t timeout = 1000;
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uint32_t reg_val;
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aic_i2c_module_disable(reg_base);
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aic_i2c_target_addr(reg_base, msg->addr);
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aic_i2c_module_enable(reg_base);
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if (!size)
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{
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aic_i2c_transmit_data_with_stop_bit(reg_base, 0);
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while (1)
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{
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reg_val = readl(reg_base + I2C_INTR_RAW_STAT);
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if (reg_val & I2C_INTR_STOP_DET)
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{
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if (reg_val & I2C_INTR_TX_ABRT)
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{
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return -1;
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}
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else
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{
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return 0;
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}
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}
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}
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}
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while (1) {
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if (size < I2C_FIFO_DEPTH) {
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for (uint16_t len = 0; len < msg->len - 1; len++) {
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aic_i2c_transmit_data(reg_base, msg->buf[len]);
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}
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aic_i2c_transmit_data_with_stop_bit(reg_base,
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msg->buf[msg->len - 1]);
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ret = aic_i2c_wait_iic_transmit(reg_base, timeout);
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if (ret != I2C_OK) {
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send_count = ret;
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break;
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}
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send_count += size;
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} else {
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while (send_count < size) {
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uint8_t send_num =
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I2C_FIFO_DEPTH - aic_i2c_get_transmit_fifo_num(reg_base);
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for (uint8_t idx = 0; idx < send_num - 1; idx++) {
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aic_i2c_transmit_data(reg_base, msg->buf[idx]);
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}
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aic_i2c_transmit_data_with_stop_bit(reg_base,
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msg->buf[msg->len - 1]);
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send_count += send_num;
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if (rt_tick_get() >= timeout) {
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ret = I2C_TIMEOUT;
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break;
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}
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}
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if (ret != I2C_OK) {
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break;
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}
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}
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if ((send_count == size) && (ret == I2C_OK)) {
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while (!(aic_i2c_get_raw_interrupt_state(reg_base) &
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I2C_INTR_STOP_DET)) {
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stop_time++;
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if (stop_time > I2C_TIMEOUT_DEF_VAL) {
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return I2C_TIMEOUT;
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}
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}
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break;
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}
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}
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return send_count;
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}
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/**
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\brief aic_i2c_master_send_msg
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\param[in] reg_base
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\param[in]
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\return state
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*/
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int32_t aic_i2c_master_receive_msg(unsigned long reg_base,
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struct rt_i2c_msg *msg)
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{
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CHECK_PARAM(msg, -EINVAL);
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int32_t ret = I2C_OK;
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uint16_t size = msg->len;
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uint32_t read_count = 0;
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uint8_t *receive_data = msg->buf;
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uint32_t timeout = 100;
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CHECK_PARAM(receive_data, -EINVAL);
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aic_i2c_module_disable(reg_base);
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aic_i2c_target_addr(reg_base, msg->addr);
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aic_i2c_module_enable(reg_base);
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if (size < I2C_FIFO_DEPTH) {
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for (uint16_t len = 0; len < size - 1; len++) {
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aic_i2c_read_data_cmd(reg_base);
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}
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aic_i2c_read_data_cmd_with_stop_bit(reg_base);
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ret = aic_i2c_wait_receive(reg_base, size, timeout);
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if (ret == I2C_OK) {
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for (read_count = 0; read_count < (int32_t)size; read_count++) {
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*(receive_data++) = aic_i2c_get_receive_data(reg_base);
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// pr_notice("receive count %d:[%02x]\n", read_count, *receive_data);
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}
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} else {
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read_count = (int32_t)ret;
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// pr_err("ret : %d\n", ret);
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}
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} else {
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read_count = 0;
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uint32_t cmd_num = 0;
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for (cmd_num = size; cmd_num > (size - I2C_FIFO_DEPTH); cmd_num--)
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aic_i2c_read_data_cmd(reg_base);
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while (read_count < size) {
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ret = aic_i2c_wait_receive(reg_base, 1U, timeout);
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if (ret != I2C_OK) {
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read_count = (int32_t)ret;
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break;
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}
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*(receive_data++) = aic_i2c_get_receive_data(reg_base);
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read_count++;
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if (cmd_num > 0U) {
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if (cmd_num == 1)
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aic_i2c_read_data_cmd_with_stop_bit(reg_base);
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else
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aic_i2c_read_data_cmd(reg_base);
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cmd_num--;
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}
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}
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uint32_t timecount = timeout + rt_tick_get();
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while (
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!(aic_i2c_get_raw_interrupt_state(reg_base) & I2C_INTR_STOP_DET)) {
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if (rt_tick_get() >= timecount) {
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ret = I2C_TIMEOUT;
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break;
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}
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}
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}
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return read_count;
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}
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