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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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96 lines
3.5 KiB
C
96 lines
3.5 KiB
C
/*
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* Copyright (c) 2024, ArtInChip Technology CO.,LTD. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Author: Chen JunLong <junlong.chen@artinchip.com>
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*/
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#ifndef _MBOX_REG_H_
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#define _MBOX_REG_H_
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#include "platform.h"
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#define MB_FIFO_DEPTH 32
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#define MB_BASE BASE_CS_MBOX_CS2SE
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#define MB_CTL_REG (MB_BASE + 0x000)
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#define MB_FIFO_CSR_REG (MB_BASE + 0x004)
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#define MB_IRQ_EN_REG (MB_BASE + 0x008)
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#define MB_IRQ_STS_REG (MB_BASE + 0x00C)
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#define MB_WMESG_REG (MB_BASE + 0x010)
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#define MB_WCOMP_REG (MB_BASE + 0x014)
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#define MB_RMESG_REG (MB_BASE + 0x018)
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#define MB_RCOMP_REG (MB_BASE + 0x01C)
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#define MB_VER_REG (MB_BASE + 0xFFC)
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#define MB_CTL_DBG_MODE_OFS (0)
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#define MB_CTL_DBG_MODE_MSK (0x1U << MB_CTL_DBG_MODE_OFS)
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#define MB_CTL_DBG_MODE_VAL(v) (((v) << MB_CTL_DBG_MODE_OFS) & MB_CTL_DBG_MODE_MSK)
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#define MB_CTL_COMP_MODE_OFS 1
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#define MB_CTL_COMP_MODE_MSK (0x1U << MB_CTL_COMP_MODE_OFS)
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#define MB_CTL_COMP_MODE_VAL(v) (((v) << MB_CTL_COMP_MODE_OFS) & MB_CTL_COMP_MODE_MSK)
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#define MB_FIFO_TF_CNT_OFS 0
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#define MB_FIFO_TF_CNT_MSK (0xFFU << MB_FIFO_TF_CNT_OFS)
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#define MB_FIFO_TF_CNT_VAL(v) (((v) << MB_FIFO_TF_CNT_OFS) & MB_FIFO_TF_CNT_MSK)
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#define MB_FIFO_TF_LVL_OFS 8
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#define MB_FIFO_TF_LVL_MSK (0x3FU << MB_FIFO_TF_LVL_OFS)
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#define MB_FIFO_TF_LVL_VAL(v) (((v) << MB_FIFO_TF_LVL_OFS) & MB_FIFO_TF_LVL_MSK)
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#define MB_FIFO_TF_OVF_CTL_OFS 14
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#define MB_FIFO_TF_OVF_CTL_MSK (0x1U << MB_FIFO_TF_OVF_CTL_OFS)
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#define MB_FIFO_TF_OVF_CTL_VAL(v) (((v) << MB_FIFO_TF_OVF_CTL_OFS) & MB_FIFO_TF_OVF_CTL_MSK)
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#define MB_FIFO_TF_RST_OFS 15
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#define MB_FIFO_TF_RST_MSK (0x1U << MB_FIFO_TF_RST_OFS)
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#define MB_FIFO_TF_RST_VAL(v) (((v) << MB_FIFO_TF_RST_OFS) & MB_FIFO_TF_RST_MSK)
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#define MB_FIFO_RF_CNT_OFS 16
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#define MB_FIFO_RF_CNT_MSK (0xFFU << MB_FIFO_RF_CNT_OFS)
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#define MB_FIFO_RF_CNT_VAL(v) (((v) << MB_FIFO_RF_CNT_OFS) & MB_FIFO_RF_CNT_MSK)
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#define MB_FIFO_RF_LVL_OFS 24
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#define MB_FIFO_RF_LVL_MSK (0x3FU << MB_FIFO_RF_LVL_OFS)
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#define MB_FIFO_RF_LVL_VAL(v) (((v) << MB_FIFO_RF_LVL_OFS) & MB_FIFO_RF_LVL_MSK)
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#define MB_FIFO_RF_RST_OFS 31
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#define MB_FIFO_RF_RST_MSK (0x1U << MB_FIFO_RF_RST_OFS)
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#define MB_FIFO_RF_RST_VAL(v) (((v) << MB_FIFO_RF_RST_OFS) & MB_FIFO_RF_RST_MSK)
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#define MB_IRQ_TF_EMP_OFS 0
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#define MB_IRQ_TF_EMP_MSK (0x1U << MB_IRQ_TF_EMP_OFS)
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#define MB_IRQ_TF_EMP_VAL(v) (((v) << MB_IRQ_TF_EMP_OFS) & MB_IRQ_TF_EMP_MSK)
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#define MB_IRQ_TF_FULL_OFS 1
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#define MB_IRQ_TF_FULL_MSK (0x1U << MB_IRQ_TF_FULL_OFS)
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#define MB_IRQ_TF_FULL_VAL(v) (((v) << MB_IRQ_TF_FULL_OFS) & MB_IRQ_TF_FULL_MSK)
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#define MB_IRQ_TF_OVF_OFS 2
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#define MB_IRQ_TF_OVF_MSK (0x1U << MB_IRQ_TF_OVF_OFS)
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#define MB_IRQ_TF_OVF_VAL(v) (((v) << MB_IRQ_TF_OVF_OFS) & MB_IRQ_TF_OVF_MSK)
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#define MB_IRQ_SLV_COMP_OFS 3
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#define MB_IRQ_SLV_COMP_MSK (0x1U << MB_IRQ_SLV_COMP_OFS)
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#define MB_IRQ_SLV_COMP_VAL(v) (((v) << MB_IRQ_SLV_COMP_OFS) & MB_IRQ_SLV_COMP_MSK)
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#define MB_IRQ_RF_EMP_OFS 8
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#define MB_IRQ_RF_EMP_MSK (0x1U << MB_IRQ_RF_EMP_OFS)
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#define MB_IRQ_RF_EMP_VAL(v) (((v) << MB_IRQ_RF_EMP_OFS) & MB_IRQ_RF_EMP_MSK)
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#define MB_IRQ_RF_FULL_OFS 9
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#define MB_IRQ_RF_FULL_MSK (0x1U << MB_IRQ_RF_FULL_OFS)
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#define MB_IRQ_RF_FULL_VAL(v) (((v) << MB_IRQ_RF_FULL_OFS) & MB_IRQ_RF_FULL_MSK)
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#define MB_IRQ_RF_UDR_OFS 10
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#define MB_IRQ_RF_UDR_MSK (0x1U << MB_IRQ_RF_UDR_OFS)
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#define MB_IRQ_RF_UDR_VAL(v) (((v) << MB_IRQ_RF_UDR_OFS) & MB_IRQ_RF_UDR_MSK)
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#define MB_IRQ_MST_COMP_OFS 11
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#define MB_IRQ_MST_COMP_MSK (0x1U << MB_IRQ_MST_COMP_OFS)
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#define MB_IRQ_MST_COMP_VAL(v) (((v) << MB_IRQ_MST_COMP_OFS) & MB_IRQ_MST_COMP_MSK)
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#endif
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