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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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74 lines
2.4 KiB
C
74 lines
2.4 KiB
C
/*
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* Copyright (c) 2024, ArtInChip Technology CO.,LTD. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Author: Chen JunLong <junlong.chen@artinchip.com>
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*/
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#ifndef __PLATFORM_H
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#define __PLATFORM_H
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#define BASE_DRAM (0x00000000)
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#define DRAM_SIZE (0x80000000UL)
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#define BASE_SP_SRAM (0x80040000)
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#define BASE_BROM (0x90000000)
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#define BASE_CS_SRAM (0x90040000)
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#define CS_SRAM_SIZE (0x00008000UL)
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#define SP_SRAM_SIZE (0x00020000UL)
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#define END_CS_SRAM (BASE_CS_SRAM + CS_SRAM_SIZE)
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#define END_SP_SRAM (BASE_SP_SRAM + SP_SRAM_SIZE)
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#define BASE_SP_USBD (0x81200000)
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#define BASE_SP_PRCM (0x88000000)
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#define BASE_SP_GPIO (0x88700000)
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#define BASE_SP_UART0 (0x88710000)
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#define BASE_SP_UART1 (0x88711000)
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#define BASE_SP_WDOG (0x89000000)
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#define BASE_SP_WRI (0x8900F000)
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#define BASE_SP_RTC (0x89030000)
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#define BASE_SP_GTC (0x89050000)
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#define BASE_DMA0 (0x91000000)
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#define BASE_DMA1 (0x91010000)
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#define BASE_DMA2 (0x91020000)
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#define BASE_DCE (0x910FF000)
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#define BASE_USBH0 (0x91210000)
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#define BASE_USBH1 (0x91220000)
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#define BASE_SPI0 (0x913F0000)
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#define BASE_SPI1 (0x91400000)
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#define BASE_SPI2 (0x91410000)
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#define BASE_SPI3 (0x91420000)
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#define BASE_SPI4 (0x91430000)
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#define BASE_SDMC0 (0x91440000)
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#define BASE_SDMC1 (0x91450000)
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#define BASE_AHBCFG (0x914FE000)
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#define BASE_CS_MBOX_CS2SP (0x91FF0000)
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#define BASE_CS_MBOX_CS2SC (0x91FF1000)
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#define BASE_CS_MBOX_CS2SE (0x91FF2000)
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#define BASE_CS_MBOX_SP2CS (0x91FF3000)
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#define BASE_CS_MBOX_SC2CS (0x91FF4000)
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#define BASE_CS_MBOX_SP2SC (0x91FF5000)
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#define BASE_CS_MBOX_SC2SP (0x91FF6000)
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#define BASE_SYSCFG (0x98000000)
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#define BASE_CMU (0x98020000)
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#define BASE_AXICFG (0x984FE000)
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#define BASE_UART0 (0x98710000)
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#define BASE_UART1 (0x98711000)
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#define BASE_UART2 (0x98712000)
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#define BASE_UART3 (0x98713000)
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#define BASE_UART4 (0x98714000)
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#define BASE_UART5 (0x98715000)
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#define BASE_WDOG (0x99000000)
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#define BASE_SID (0x99010000)
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#define BASE_SE_SRAM (0xF0040000)
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#define SE_SRAM_SIZE (0x00018000UL)
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#define END_SE_SRAM (BASE_SE_SRAM + SE_SRAM_SIZE)
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#define IS_SESS_SRAM(x) (((unsigned long)(x) >= BASE_SE_SRAM) && ((unsigned long)(x) < END_SE_SRAM))
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#define IS_CSYS_SRAM(x) (((unsigned long)(x) >= BASE_CS_SRAM) && ((unsigned long)(x) < END_CS_SRAM))
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#define IS_SPSS_SRAM(x) (((unsigned long)(x) >= BASE_SP_SRAM) && ((unsigned long)(x) < END_SP_SRAM))
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#endif
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