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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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252 lines
6.2 KiB
C
252 lines
6.2 KiB
C
/*
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* Copyright (c) 2023-2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _DISP_CONF_H_
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#define _DISP_CONF_H_
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/**
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* LVDS options
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*/
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#include <aic_hal_lvds.h>
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/* lvds sync mode enable */
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#define AIC_LVDS_SYNC_MODE_EN 1
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/* lvds link swap enable, swap lvds link0 and link1 */
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#define AIC_LVDS_LINK_SWAP_EN 0
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/**
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* lvds channel output order
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*
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* link 0 default D3 CK D2 D1 D0
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* PD26/PD27 PD24/PD25 PD22/PD23 PD20/PD21 PD18/PD19
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*
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* link 1 default D3 CK D2 D1 D0
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* PD16/PD17 PD14/PD15 PD12/PD13 PD10/PD11 PD8/PD9
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*
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*
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* link 0 example:
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* D2 CK D3 D1 D0
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* PD26/PD27 PD24/PD25 PD22/PD23 PD20/PD21 PD18/PD19
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*
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* AIC_LVDS_LINK0_LANES LVDS_LANES(LVDS_D2, LVDS_CK, LVDS_D3, LVDS_D1, LVDS_D0)
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* link1 example is the same as link0
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*/
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#define AIC_LVDS_LINK0_LANES LVDS_LANES(LVDS_D3, LVDS_CK, LVDS_D2, LVDS_D1, LVDS_D0)
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#define AIC_LVDS_LINK1_LANES LVDS_LANES(LVDS_D3, LVDS_CK, LVDS_D2, LVDS_D1, LVDS_D0)
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/**
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* lvds channel polarities
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*
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* link 0 default PD26/PD27 PD24/PD25 PD22/PD23 PD20/PD21 PD18/PD19
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* N/P N/P N/P N/P N/P
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*
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* link 1 default PD16/PD17 PD14/PD15 PD12/PD13 PD10/PD11 PD8/PD9
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* N/P N/P N/P N/P N/P
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*
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*
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* link 0 example:
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* PD26/PD27 PD24/PD25 PD22/PD23 PD20/PD21 PD18/PD19
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* N/P P/N N/P P/N N/P
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*
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* AIC_LVDS_LINK0_POL 0b01010
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* link1 example is the same as link0
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*/
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#define AIC_LVDS_LINK0_POL 0b00000
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#define AIC_LVDS_LINK1_POL 0b00000
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/**
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* lvds channel phy config
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*/
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#define AIC_LVDS_LINK0_PHY 0xFA
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#define AIC_LVDS_LINK1_PHY 0xFA
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/**
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* MIPI-DSI options
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*/
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/**
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* data lane assignments
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*
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* default D3 D2 D1 D0
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* PD26/PD27 PD24/PD25 PD22/PD23 PD19/PD20
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*
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* example D0 D1 D2 D3
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* PD26/PD27 PD24/PD25 PD22/PD23 PD19/PD20
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*
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* LANE_ASSIGNMENTS 0x0123
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*/
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#define LANE_ASSIGNMENTS 0x3210
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/**
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* data lane polarities
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*
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* default PD26/PD27 PD24/PD25 PD22/PD23 PD19/PD20
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* N/P N/P N/P N/P
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*
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* example PD26/PD27 PD24/PD25 PD22/PD23 PD19/PD20
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* P/N N/P P/N N/P
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*
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* LANE_POLARITIES 0b1010
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*/
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#define LANE_POLARITIES 0b0000
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/**
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* data clk inverse
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*
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* default PD24/PD25
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* N/P
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*
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* CLK_INVERSE 1 PD24/PD25
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* P/N
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*/
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#define CLK_INVERSE 0
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/* virtual channel id */
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#define VIRTUAL_CHANNEL 0
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/* mipi-dsi lp rate, range [10M, 20M], default 10M */
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#define MIPI_DSI_LP_RATE (10 * 1000 * 1000)
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/* mipi-dsi dcs get display id from screen when panel enable */
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#define DCS_GET_DISPLAY_ID 0
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/**
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* FB ROTATION options
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*/
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/* drawing buf for GUI, range [1, 2] */
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#define AIC_FB_DRAW_BUF_NUM 2
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/**
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* Display Engine options
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*/
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/* display flags, config hsync/vsync polarities */
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#define AIC_DISPLAY_FLAGS (DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW)
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/**
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* Display Engine Mode
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*
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* Continue mode, ignore the TE signal of LCD and the timing signal
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* of display engine is continuous.
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*
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* Single frame mode, the timing signal of display engine needs to be
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* manually updated.
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*
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* Auto mode, need a TE pulse width. The display engine automatically
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* updates timing signal after obtained a TE signal from LCD.
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*
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* If unsure, say continuous mode.
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*/
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#define CONTINUE 0
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#define SINGLE 1
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#define AUTO 2
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#define DE_MODE CONTINUE
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/**
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* AUTO mode options
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*/
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#if ( DE_MODE == 2 )
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# define DE_AUTO_MODE 1
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#endif
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#if DE_AUTO_MODE
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/**
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* TE PIN
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*
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* D12x, just support { "PC.6", "PD.2", "PF.15" }
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* D13x, just support { "PC.6", "PA.1" }
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*/
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# define TE_PIN "PC.6"
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# define TE_PULSE_WIDTH 2
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#endif
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#ifdef AIC_DISP_PQ_TOOL
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#define PANEL_PIXELCLOCK 70
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#define PANEL_HACTIVE 800
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#define PANEL_HBP 150
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#define PANEL_HFP 160
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#define PANEL_HSW 20
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#define PANEL_VACTIVE 1280
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#define PANEL_VBP 12
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#define PANEL_VFP 20
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#define PANEL_VSW 2
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#define AIC_RGB_MODE PRGB
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#define AIC_RGB_FORMAT PRGB_18BIT_HD
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#define AIC_RGB_CLK_CTL DEGREE_0
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#define AIC_RGB_DATA_ORDER RGB
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#define AIC_RGB_DATA_MIRROR 0
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#define AIC_LVDS_MODE NS
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#define AIC_LVDS_LINK_MODE SINGLE_LINK0
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#define AIC_MIPI_DSI_MODE DSI_MOD_VID_BURST
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#define AIC_MIPI_DSI_FORMAT DSI_FMT_RGB888
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#define AIC_MIPI_DSI_LINE_NUM 4
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#define AIC_PANEL_ENABLE_GPIO "PE.19"
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#define PANEL_RESET 0
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#if PANEL_RESET
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#define AIC_PANEL_RESET_GPIO "PE.6"
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#endif
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struct disp_pinmux {
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unsigned char func;
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unsigned char bias;
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unsigned char drive;
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char *name;
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};
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#define AIC_PQ_TOOL_SET_DISP_PINMUX_FOPS(disp_pin) \
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static void aic_set_disp_pinmux_for_pq_tool(void)\
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{\
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uint32_t i = 0;\
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long pin = 0;\
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unsigned int g;\
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unsigned int p;\
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\
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for (i = 0; i < ARRAY_SIZE(disp_pin); i++) {\
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pin = hal_gpio_name2pin(disp_pin[i].name);\
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if (pin < 0)\
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continue;\
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g = GPIO_GROUP(pin);\
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p = GPIO_GROUP_PIN(pin);\
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hal_gpio_set_func(g, p, disp_pin[i].func);\
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hal_gpio_set_bias_pull(g, p, disp_pin[i].bias);\
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hal_gpio_set_drive_strength(g, p, disp_pin[i].drive);\
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}\
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}
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#define AIC_PQ_SET_DSIP_PINMUX \
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aic_set_disp_pinmux_for_pq_tool()
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#define AIC_PQ_TOOL_PINMUX_CONFIG(name) \
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static struct disp_pinmux name[] = { \
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{3, PIN_PULL_DIS, 3, "PD.8"},\
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{3, PIN_PULL_DIS, 3, "PD.9"},\
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{3, PIN_PULL_DIS, 3, "PD.10"},\
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{3, PIN_PULL_DIS, 3, "PD.11"},\
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{3, PIN_PULL_DIS, 3, "PD.12"},\
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{3, PIN_PULL_DIS, 3, "PD.13"},\
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{3, PIN_PULL_DIS, 3, "PD.14"},\
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{3, PIN_PULL_DIS, 3, "PD.15"},\
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{3, PIN_PULL_DIS, 3, "PD.16"},\
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{3, PIN_PULL_DIS, 3, "PD.17"},\
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}
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#define PANEL_DSI_SIMEP_SEND_SEQ \
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panel_dsi_dcs_send_seq(panel, 0x00); \
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#endif
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#endif /* _DISP_CONF_H_ */
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