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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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290 lines
6.8 KiB
ArmAsm
290 lines
6.8 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023-2024, ArtInChip Technology Co., Ltd
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*
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* Authors:
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* dwj <weijie.ding@artinchip.com>
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*/
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//# include <sbi/riscv_asm.h>
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#define DDRC_BASE 0x18400000
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#define DDR_PHY_BASE 0x18500000
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#define GTC_CNTV 0x19050008
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#define CMU_DDR_REG 0x18020210
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#define CMU_PLL_INT1_REG 0x18020004
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#define CMU_PLL_FRA0_REG 0x18020020
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#define CMU_PLL_IN_REG 0x180200A4
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#define SYSCFG_LDO25_REG 0x18000024
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.macro delay_200us
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li a0, GTC_CNTV
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ld a1, (a0) //start value 64bit
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1:
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ld a2, (a0) //current value 64bit
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sub a3, a2, a1 //t3 <--- t2 - t1
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li a4, 800 //GTC frequency is 4000000Hz, 200us counter 800
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bltu a3, a4, 1b
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2:
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.endm
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.section .entry, "ax", %progbits
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.align 3
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.option pic
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.global aic_suspend_resume
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aic_suspend_resume:
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//ddr self-refresh flow
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li t0, DDRC_BASE
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li t1, DDR_PHY_BASE
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//check port status
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check_port_status:
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lw t2, 0x3fc(t0)
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bne t2, zero, check_port_status
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//disable DDR port
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li t2, 0
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li t3, 0
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li t5, 5
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addi t0, t0, 0x490
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port_close_loop:
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add t0, t0, t2
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sw zero, (t0)
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addi t2, t2, 0xb0
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addi t3, t3, 1
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bltu t3, t5, port_close_loop
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delay_200us
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//enter self refresh
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li t0, DDRC_BASE
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lw t2, 0x30(t0)
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ori t2, t2, 0x21
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sw t2, 0x30(t0)
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check_ddr_enter_sr_status:
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lw t2, 0x4(t0)
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andi t2, t2, 0x3
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li t3, 0x3
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bne t2, t3, check_ddr_enter_sr_status
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delay_200us
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//en_dfi_dram_clk_disable
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lw t2, 0x30(t0)
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ori t2, t2, 0x8
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sw t2, 0x30(t0)
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//disable PGCR0 reg CKEN bitfiled
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lw t2, 0x8(t1)
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li t3, 0x3ffffff
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and t2, t2, t3
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sw t2, 0x8(t1)
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delay_200us
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//disable DX0GCR reg DQ, DM, DQS
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lw t2, 0x1C0(t1)
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ori t2, t2, 0x30
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li t3, 0xffff3fff
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and t2, t2, t3
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li t3, 0x8000
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or t2, t2, t3
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sw t2, 0x1C0(t1)
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//disable DX1GCR reg DQ, DM, DQS
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lw t2, 0x200(t1)
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ori t2, t2, 0x30
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li t3, 0xffff3fff
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and t2, t2, t3
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li t3, 0x8000
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or t2, t2, t3
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sw t2, 0x200(t1)
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//disable DDR phy/bus clock
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li t1, CMU_DDR_REG
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lw t2, (t1)
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li t3, 0xfffaabff
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and t2, t2, t3
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sw t2, (t1)
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delay_200us
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//disable DDR phy update request
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li t1, DDR_PHY_BASE
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lw t2, 0x40(t1)
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li t3, 0xfffffffe
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and t2, t2, t3
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sw t2, 0x40(t1)
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//disable DDR core controller clock
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li t1, CMU_DDR_REG
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lw t2, (t1)
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li t3, 0xfffffeff
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and t2, t2, t3
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sw t2, (t1)
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delay_200us
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//disable PLL_FRA0
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li t1, CMU_PLL_FRA0_REG
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lw t2, (t1)
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li t3, 0xfffaffff
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and t2, t2, t3
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sw t2, (t1)
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//disable PLL_INT1
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li t1, CMU_PLL_INT1_REG
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lw t2, (t1)
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li t3, 0xfffaffff
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and t2, t2, t3
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sw t2, (t1)
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//disable XTAL_GM and XTAL_START
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li t1, CMU_PLL_IN_REG
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lw t2, (t1)
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li t3, 0x1fffffff
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and t2, t2, t3
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sw t2, (t1)
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//disable LDO25
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li t1, SYSCFG_LDO25_REG
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lw t2, (t1)
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li t3, 0xfffffff7
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and t2, t2, t3
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sw t2, (t1)
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wfi
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//wakeup flow
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//enable LDO25
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li t1, SYSCFG_LDO25_REG
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lw t2, (t1)
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li t3, 0x8
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or t2, t2, t3
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sw t2, (t1)
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//enable XTAL_GM and XTAL_START
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li t1, CMU_PLL_IN_REG
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lw t2, (t1)
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li t3, 0xe0000000
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or t2, t2, t3
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sw t2, (t1)
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//enable PLL_INT1
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li t1, CMU_PLL_INT1_REG
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lw t2, (t1)
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li t3, 0x50000
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or t2, t2, t3
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sw t2, (t1)
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//enable PLL_FRA0
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li t1, CMU_PLL_FRA0_REG
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lw t2, (t1)
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li t3, 0x50000
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or t2, t2, t3
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sw t2, (t1)
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delay_200us
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//enable DDR phy/bus clock
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li t1, CMU_DDR_REG
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lw t2, (t1)
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li t3, 0x55400
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or t2, t2, t3
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sw t2, (t1)
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delay_200us
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//enable DDR phy update request
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li t1, DDR_PHY_BASE
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lw t2, 0x40(t1)
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ori t2, t2, 0x1
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sw t2, 0x40(t1)
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//enable DDR core controller clock
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li t1, CMU_DDR_REG
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lw t2, (t1)
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ori t2, t2, 0x100
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sw t2, (t1)
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//must reset PLL if the DDR core clock disabled in self-refresh state
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li t0, DDRC_BASE
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li t1, DDR_PHY_BASE
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lw t2, 0x18(t1)
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li t3, 0x40000000
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or t2, t2, t3
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sw t2, 0x18(t1)
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delay_200us
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li t3, 0xbfffffff
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and t2, t2, t3
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sw t2, 0x18(t1)
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delay_200us
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//enable dfi_dram_clk
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lw t2, 0x30(t0)
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li t3, 0xFFFFFFF7
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and t2, t2, t3
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sw t2, 0x30(t0)
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//enable PGCR0 reg CKEN bitfiled
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lw t2, 0x8(t1)
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li t3, 0x3ffffff
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and t2, t2, t3
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li t3, 0x8000000
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or t2, t2, t3
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sw t2, 0x8(t1)
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delay_200us
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//enable DX0GCR reg DQ, DM, DQS
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lw t2, 0x1C0(t1)
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li t3, 0xFFFF3FCF
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and t2, t2, t3
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sw t2, 0x1C0(t1)
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//enable DX1GCR reg DQ, DM, DQS
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lw t2, 0x200(t1)
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li t3, 0xFFFF3FCF
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and t2, t2, t3
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sw t2, 0x200(t1)
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delay_200us
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//DDR exit self-refresh
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lw t2, 0x30(t0)
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li t3, 0xDE
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and t2, t2, t3
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sw t2, 0x30(t0) //exit self-refresh
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check_ddr_exit_sr_status:
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lw t2, 0x4(t0)
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andi t2, t2, 0x3
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li t3, 0x1
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bne t2, t3, check_ddr_exit_sr_status
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delay_200us
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li t2, 0
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li t3, 0
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li t4, 1
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li t5, 5
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addi t0, t0, 0x490
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port_open_loop:
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add t0, t0, t2
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sw t4, (t0)
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addi t2, t2, 0xb0
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addi t3, t3, 1
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bltu t3, t5, port_open_loop
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ret
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aic_suspend_resume_end:
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.data
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.align 3
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.global aic_suspend_resume_size
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aic_suspend_resume_size:
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.word aic_suspend_resume_end - aic_suspend_resume
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