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278 lines
7.4 KiB
ArmAsm
278 lines
7.4 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023-2024, ArtInChip Technology Co., Ltd
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*
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* Authors:
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* dwj <weijie.ding@aic.com>
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*/
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#include <rtconfig.h>
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#define DDRC_BASE 0x98400000
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#define DDR_PHY_BASE 0x98500000
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#define GTC_CNTVL 0x89050008
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#define GTC_CNTVH 0x8905000C
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#define PRCM_SW_VDD11_CTL 0x88000070
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#define PRCM_C908_VDD11_CTL 0x88000074
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#define PRCM_DDR_WAKEUP_STATUS 0x88000108
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.macro delay_200us
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li s0, GTC_CNTVL
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li s1, GTC_CNTVH
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lw s2, (s0) //start value 32bit low
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lw s3, (s1) //start value 32bit high
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1:
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lw s4, (s0) //current value 32bit low
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lw s5, (s1) //current value 32bit high
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sub s6, s4, s2 //s6 save 32bit low of sub
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sltu s7, s4, s6 //s7 save carry
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sub s8, s5, s3 //s8 save 32bit high of sub
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sub s8, s8, s7 //s8 sub carry
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bnez s8, 2f
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li s4, 800 //GTC frequency is 4000000Hz, 200us counter 800
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bltu s6, s4, 1b
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2:
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.endm
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.section .entry, "ax", %progbits
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.align 3
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.option pic
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.global aic_suspend_resume
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aic_suspend_resume:
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//step1: DDR enter self refresh
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//ddr self-refresh flow
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li t0, DDRC_BASE
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li t1, DDR_PHY_BASE
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//disable DDR port
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li t2, 0
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li t3, 0
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li t5, 5
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addi t0, t0, 0x490
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port_close_loop:
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add t0, t0, t2
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sw zero, (t0)
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addi t2, t2, 0xb0
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addi t3, t3, 1
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bltu t3, t5, port_close_loop
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//enter self refresh
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li t0, DDRC_BASE
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lw t1, 0x30(t0)
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ori t1, t1, 0x21
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sw t1, 0x30(t0)
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#ifndef FPGA_BOARD_ARTINCHIP
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delay_200us
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//step2: C908 VDD11 power down
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li t0, PRCM_C908_VDD11_CTL
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lw t1, (t0)
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li t2, 0xFFFEFFFF
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and t1, t1, t2
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li t3, 0x27000000
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or t1, t1, t3 //C908 VDD11 key
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sw t1, (t0) //clear PMU_RESET
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delay_200us
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li t2, 0x8000
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or t1, t1, t2
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sw t1, (t0) //set ISO_ENABLE
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delay_200us
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PD_C908_check:
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lw t1, (t0)
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li t2, 0x100
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and t3, t1, t2
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bnez t3, PD_C908_check //check POWER_SWITCH_D_STATUS
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//step3: VDD11 SW power down
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//Power down flow
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li t0, PRCM_SW_VDD11_CTL
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lw t1, (t0)
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li t2, 0xFFFEFFFF
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and t1, t1, t2
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li t3, 0x27000000
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or t1, t1, t3 //VDD11 SW key
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sw t1, (t0) //clear PMU_RESET
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delay_200us
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li t2, 0x8000
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or t1, t1, t2
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sw t1, (t0) //set ISO_ENABLE
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delay_200us
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li t2, 0xFFFFBFFF
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and t1, t1, t2
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sw t1, (t0) //clear DDR_RETENTION_EN
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delay_200us
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li t2, 0xFFFFDFFF
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and t1, t1, t2
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sw t1, (t0) //clear SRAM_RETENTION_EN_PRE
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delay_200us
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li t2, 0xFFFFEFFF
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and t1, t1, t2
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sw t1, (t0) //clear SRAM_RETENTION_EN
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delay_200us
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PD_PSD_check:
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lw t1, (t0)
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li t2, 0x200
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and t3, t1, t2
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bnez t3, PD_PSD_check //check POWER_SWITCH_D_STATUS
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PD_PSA_check:
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lw t1, (t0)
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li t2, 0x100
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and t3, t1, t2
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bnez t3, PD_PSA_check //check POWER_SWITCH_A_STATUS
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li t2, 0xFFFFFF7F
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit7
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delay_200us
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li t2, 0xFFFFFFBF
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit6
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delay_200us
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li t2, 0xFFFFFFDF
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit5
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delay_200us
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li t2, 0xFFFFFFEF
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit4
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delay_200us
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li t2, 0xFFFFFFF7
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit3
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delay_200us
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li t2, 0xFFFFFFFB
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit2
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delay_200us
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li t2, 0xFFFFFFFD
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit1
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delay_200us
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li t2, 0xFFFFFFFE
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and t1, t1, t2
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sw t1, (t0) //clear POWER_SWITCH_EN[7:0] bit0
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delay_200us
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#endif
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//enter wfi
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wfi
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#ifndef FPGA_BOARD_ARTINCHIP
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//step1: VDD11 SW power up
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li t0, PRCM_SW_VDD11_CTL
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lw t1, (t0)
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li t2, 0x27000001
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit0 with VDD11 key
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delay_200us
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li t2, 0x2
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit1
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delay_200us
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li t2, 0x4
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit2
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delay_200us
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li t2, 0x8
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit3
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delay_200us
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li t2, 0x10
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit4
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delay_200us
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li t2, 0x20
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit5
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delay_200us
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li t2, 0x40
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit6
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delay_200us
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li t2, 0x80
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or t1, t1, t2
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sw t1, (t0) //set POWER_SWITCH_EN[7:0] bit7
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delay_200us
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PU_PSA_check:
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lw t1, (t0)
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li t2, 0x100
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and t3, t1, t2
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beqz t3, PU_PSA_check //check POWER_SWITCH_A_STATUS
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PU_PSD_check:
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lw t1, (t0)
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li t2, 0x200
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and t3, t1, t2
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beqz t3, PU_PSD_check //check POWER_SWITCH_A_STATUS
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li t2, 0x1000
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or t1, t1, t2
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sw t1, (t0) //set SRAM_RETENTION_EN
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delay_200us
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li t2, 0x2000
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or t1, t1, t2
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sw t1, (t0) //set SRAM_RETENTION_EN_PRE
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delay_200us
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li t2, 0x4000
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or t1, t1, t2
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sw t1, (t0) //set DDR_RETENTION_EN
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delay_200us
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li t2, 0xFFFF7FFF
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and t1, t1, t2
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sw t1, (t0) //clear ISO_ENABLE
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delay_200us
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li t2, 0x10000
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or t1, t1, t2
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// set PMU_RESET, SESS will boot
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sw t1, (t0) //set PMU_RESET
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delay_200us
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//step2: C908 VDD11 power up
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li t0, PRCM_C908_VDD11_CTL
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PU_C908_check:
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lw t1, (t0)
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li t2, 0x100
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and t3, t1, t2
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beqz t3, PU_C908_check
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li t2, 0xFFFF7FFF
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and t1, t1, t2
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sw t1, (t0) //clear ISO_ENABLE
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delay_200us
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li t2, 0x10000
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or t1, t1, t2
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sw t1, (t0) //set PMU_RESET
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delay_200us
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#endif
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//step3: DDR exit self-refresh
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li t0, DDRC_BASE
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li t1, DDR_PHY_BASE
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lw t1, 0x30(t0)
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li t2, 0xDE
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and t1, t1, t2
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sw t1, 0x30(t0) //exit self-refresh
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li t2, 0
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li t3, 0
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li t4, 1
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li t5, 5
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addi t0, t0, 0x490
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port_open_loop:
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add t0, t0, t2
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sw t4, (t0)
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addi t2, t2, 0xb0
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addi t3, t3, 1
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bltu t3, t5, port_open_loop
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.long 0x0100000b //icache.iall
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.long 0x0010000b //dcache.call
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ret
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aic_suspend_resume_end:
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.data
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.align 3
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.global aic_suspend_resume_size
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aic_suspend_resume_size:
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.word aic_suspend_resume_end - aic_suspend_resume
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