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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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166 lines
3.8 KiB
ArmAsm
166 lines
3.8 KiB
ArmAsm
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023-2024, ArtInChip Technology Co., Ltd
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*
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* Authors:
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* dwj <weijie.ding@aic.com>
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*/
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#define PRCM_SCSS_CPU_STATUS 0x88000110
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#define PRCM_SC_CONTEXT_ADDR 0x8800011c
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.section .entry, "ax", %progbits
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.align 3
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.option pic
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.global sc_save_context_and_suspend
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sc_save_context_and_suspend:
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sw ra, 0(a0)
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sw sp, 4(a0)
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sw gp, 8(a0)
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sw tp, 0xc(a0)
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sw s0, 0x10(a0)
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sw s1, 0x14(a0)
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sw a1, 0x18(a0)
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sw a2, 0x1c(a0)
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sw a3, 0x20(a0)
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sw a4, 0x24(a0)
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sw a5, 0x28(a0)
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sw a6, 0x2c(a0)
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sw a7, 0x30(a0)
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sw s2, 0x34(a0)
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sw s3, 0x38(a0)
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sw s4, 0x3c(a0)
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sw s5, 0x40(a0)
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sw s6, 0x44(a0)
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sw s7, 0x48(a0)
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sw s8, 0x4c(a0)
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sw s9, 0x50(a0)
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sw s10, 0x54(a0)
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sw s11, 0x58(a0)
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/* save CSRs */
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csrr t0, mepc
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sw t0, 0x5c(a0)
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csrr t0, mstatus
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sw t0, 0x60(a0)
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csrr t0, mtval
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sw t0, 0x64(a0)
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csrr t0, mcause
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sw t0, 0x68(a0)
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csrr t0, mie
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sw t0, 0x6c(a0)
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csrr t0, mtvec
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sw t0, 0x70(a0)
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csrr t0, mtvt
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sw t0, 0x74(a0)
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csrr t0, mscratch
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sw t0, 0x78(a0)
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csrr t0, mxstatus
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sw t0, 0x7c(a0)
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csrr t0, mhcr
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sw t0, 0x80(a0)
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csrr t0, mhint
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sw t0, 0x84(a0)
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csrr t0, mexstatus
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sw t0, 0x88(a0)
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/* save sc context addr to PRCM_SC_CONTEXT_ADDR */
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li t0, PRCM_SC_CONTEXT_ADDR
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sw a0, (t0)
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/* Update CPU status to PRCM bank register */
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li t0, PRCM_SCSS_CPU_STATUS
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li t1, 1
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sw t1, (t0)
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fence.i
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fence
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sync.i
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sync
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wfi
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ret
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sc_save_context_and_suspend_end:
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.data
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.align 3
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.global sc_save_context_and_suspend_size
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sc_save_context_and_suspend_size:
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.word sc_save_context_and_suspend_end - sc_save_context_and_suspend
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.section .entry, "ax", %progbits
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.align 3
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.option pic
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.global sc_restore_context_and_resume
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sc_restore_context_and_resume:
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li t0, PRCM_SC_CONTEXT_ADDR
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lw a0, (t0)
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lw ra, 0(a0)
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lw sp, 4(a0)
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lw gp, 8(a0)
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lw tp, 0xc(a0)
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lw s0, 0x10(a0)
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lw s1, 0x14(a0)
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lw a1, 0x18(a0)
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lw a2, 0x1c(a0)
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lw a3, 0x20(a0)
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lw a4, 0x24(a0)
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lw a5, 0x28(a0)
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lw a6, 0x2c(a0)
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lw a7, 0x30(a0)
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lw s2, 0x34(a0)
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lw s3, 0x38(a0)
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lw s4, 0x3c(a0)
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lw s5, 0x40(a0)
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lw s6, 0x44(a0)
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lw s7, 0x48(a0)
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lw s8, 0x4c(a0)
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lw s9, 0x50(a0)
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lw s10, 0x54(a0)
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lw s11, 0x58(a0)
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/* restore CSRs */
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lw t0, 0x5c(a0)
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csrw mepc, t0
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lw t0, 0x60(a0)
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csrw mstatus, t0
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lw t0, 0x64(a0)
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csrw mtval, t0
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lw t0, 0x68(a0)
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csrw mcause, t0
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lw t0, 0x6c(a0)
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csrw mie, t0
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lw t0, 0x70(a0)
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csrw mtvec, t0
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lw t0, 0x74(a0)
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csrw mtvt, t0
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lw t0, 0x78(a0)
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csrw mscratch, t0
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lw t0, 0x7c(a0)
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csrw mxstatus, t0
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lw t0, 0x80(a0)
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csrw mhcr, t0
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lw t0, 0x84(a0)
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csrw mhint, t0
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lw t0, 0x88(a0)
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csrw mexstatus, t0
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/* clear sc context addr to 0 in PRCM_SC_CONTEXT_ADDR */
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li t0, PRCM_SC_CONTEXT_ADDR
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sw zero, (t0)
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/* clear CPU status to PRCM bank register */
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li t0, PRCM_SCSS_CPU_STATUS
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sw zero, (t0)
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ret
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sc_restore_context_and_resume_end:
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.data
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.align 3
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.global sc_restore_context_and_resume_size
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sc_restore_context_and_resume_size:
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.word sc_restore_context_and_resume_end - sc_restore_context_and_resume
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