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363 lines
12 KiB
C
363 lines
12 KiB
C
/*
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* Copyright (c) 2022-2024, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Xiong Hao <hao.xiong@artinchip.com>
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*/
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#ifndef _AIC_MMC_H_
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#define _AIC_MMC_H_
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#include <aic_core.h>
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#include <hal_sdmc.h>
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#include <aic_partition.h>
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struct aic_sdmc_pdata {
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ulong base;
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int irq;
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int clk;
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int clk_freq;
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u32 is_sdio;
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u8 id;
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u8 buswidth;
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u8 drv_phase;
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u8 smp_phase;
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};
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struct aic_sdmc_dev {
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void *priv;
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u32 voltages;
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u32 version;
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u32 freq_min;
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u32 freq_max;
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u32 high_capacity;
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u32 bus_width;
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u32 clock;
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u32 card_caps;
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u32 card_capacity; /* unit: KB*/
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u32 host_caps;
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u32 valid_ocr;
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u32 scr[2];
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u32 rca;
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u32 part_config;
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u32 boot_bus_cond;
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u32 part_num;
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u32 read_bl_len;
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u32 erase_grp_size; /* in 512-byte sectors */
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u32 blk_max;
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u32 sdmc_id;
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u32 max_seg_size;
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u32 max_dma_segs;
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u32 max_blk_size;
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u32 max_blk_count;
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u32 flags;
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};
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struct aic_sdmc_cmd {
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u32 cmd_code;
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u32 resp_type;
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u32 arg;
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u32 resp[4];
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u32 flags;
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u32 auto_stop_flag;
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int err;
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};
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struct aic_sdmc_data {
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u8 *buf;
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u32 flags;
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u32 blks;
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u32 blksize;
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int err;
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};
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/**
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* struct aic_sdmc - Information about a ArtInChip SDMC host
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*
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* @quirks: Quick flags - see SDMC_QUIRK_...
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* @caps: Capabilities - see MMC_MODE_...
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* @sclk_rate: The rate of SDMC clk in Hz. It's the basis clk for SDMC.
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* @div: Clock divider value for use by controller
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* @buswidth: Bus width in bits (8 or 4)
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*/
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struct aic_sdmc {
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struct aic_sdmc_dev *dev;
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struct aic_sdmc_cmd *cmd;
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struct aic_sdmc_data *data;
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struct aic_sdmc_host host;
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u32 *buf;
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u32 clk;
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u32 irq;
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u32 index;
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u32 cid[4];
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unsigned int quirks;
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unsigned int caps;
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unsigned int version;
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unsigned int clock;
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unsigned int sclk_rate;
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unsigned int div;
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int ddr_mode;
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/* use fifo mode to read and write data */
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int fifo_mode;
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struct aic_sdmc_pdata *pdata;
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};
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/* Maximum block size for MMC */
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#define MMC_MAX_BLOCK_LEN 512
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/*
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* The number of MMC physical partitions. These consist of:
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* boot partitions (2), general purpose partitions (4) in MMC v4.4.
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*/
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#define MMC_NUM_BOOT_PARTITION 2
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#define MMC_PART_RPMB 3 /* RPMB partition number */
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#define SD_VERSION_SD 0x20000
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#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
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#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
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#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
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#define MMC_VERSION_MMC 0x10000
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#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
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#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
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#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
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#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
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#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
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#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
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#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x41)
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#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x42)
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#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x43)
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#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x44)
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#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x45)
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#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x50)
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#define MMC_VERSION_5_1 (MMC_VERSION_MMC | 0x51)
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#define MMC_MODE_HS 0x001
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#define MMC_MODE_HS_52MHz 0x010
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#define MMC_MODE_4BIT 0x100
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#define MMC_MODE_8BIT 0x200
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#define MMC_MODE_SPI 0x400
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#define MMC_MODE_HC 0x800
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#define SD_DATA_4BIT 0x00040000
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#define IS_SD(x) (x->dev->version & SD_VERSION_SD)
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#define MMC_CMD_BOOT 1
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#define MMC_CMD_BOOT_ABORT 2
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#define MMC_AUTO_STOP 1
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#define MMC_DATA_READ 1
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#define MMC_DATA_WRITE 2
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#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
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#define UNUSABLE_ERR -17 /* Unusable Card */
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#define COMM_ERR -18 /* Communications Error */
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#define TIMEOUT -19
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#define MMC_CMD_GO_IDLE_STATE 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RELATIVE_ADDR 3
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#define MMC_CMD_SET_DSR 4
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#define MMC_CMD_SWITCH 6
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#define MMC_CMD_SELECT_CARD 7
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#define MMC_CMD_SEND_EXT_CSD 8
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_STOP_TRANSMISSION 12
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_SINGLE_BLOCK 17
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18
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#define MMC_CMD_SET_BLOCK_COUNT 23
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
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#define MMC_CMD_ERASE_GROUP_START 35
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#define MMC_CMD_ERASE_GROUP_END 36
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#define MMC_CMD_ERASE 38
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#define MMC_CMD_APP_CMD 55
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#define MMC_CMD_SPI_READ_OCR 58
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#define MMC_CMD_SPI_CRC_ON_OFF 59
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#define SD_CMD_SEND_RELATIVE_ADDR 3
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#define SD_CMD_SWITCH_FUNC 6
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#define SD_CMD_SEND_IF_COND 8
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#define SD_CMD_APP_SET_BUS_WIDTH 6
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#define SD_CMD_ERASE_WR_BLK_START 32
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#define SD_CMD_ERASE_WR_BLK_END 33
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#define SD_CMD_APP_SEND_OP_COND 41
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#define SD_CMD_APP_SEND_SCR 51
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/* SCR definitions in different words */
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#define SD_HIGHSPEED_BUSY 0x00020000
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#define SD_HIGHSPEED_SUPPORTED 0x00020000
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#define MMC_HS_TIMING 0x00000100
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#define MMC_HS_52MHZ 0x2
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#define OCR_BUSY 0x80000000
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#define OCR_HCS 0x40000000
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#define OCR_VOLTAGE_MASK 0x00FFFF80
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#define OCR_ACCESS_MODE 0x60000000
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#define MMC_ERASE_ARG 0x00000000
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#define MMC_SECURE_ERASE 0x80000000
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#define MMC_STATUS_MASK (~0x0206BF7F)
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#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
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#define MMC_STATUS_CURR_STATE (0xf << 9)
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#define MMC_STATUS_ERROR (1 << 19)
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
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#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
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#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
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#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
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#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
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#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
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#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
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#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
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#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
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#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
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#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
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#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte addressed by index which are 1 in value field */
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#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte addressed by index, which are 1 in value field */
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#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
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#define SD_SWITCH_CHECK 0
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#define SD_SWITCH_SWITCH 1
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#define SD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define SD_BUS_WIDTH_4 2 /* Card is in 4 bit mode */
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
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#define EXT_CSD_BOOT_BUS_COND 177 /* R/W */
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#define EXT_CSD_PART_CONF 179 /* R/W */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
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#define EXT_CSD_CMD_SET_SECURE (1 << 1)
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#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
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#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
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#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
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#define EXT_CSD_BUS_WIDTH_4 (1 << 0) /* Card is in 4 bit mode */
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#define EXT_CSD_BUS_WIDTH_8 (1 << 1) /* Card is in 8 bit mode */
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#define EXT_CSD_MUTBLKWRITE (1 << 2)
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#define EXT_CSD_SUP_SDIO_IRQ (1 << 4) /* support signal pending SDIO IRQs */
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#define EXT_CSD_SUP_HIGHSPEED (1 << 5) /* support high speed */
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#define EXT_CSD_SUP_HIGHSPEED_DDR (1 << 6) /* support high speed(DDR) */
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#define EXT_CSD_SUP_HIGHSPEED_HS200 (1 << 7) /* support high speed HS200 */
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#define EXT_CSD_SUP_HIGHSPEED_HS400 (1 << 8) /* support high speed HS400 */
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#define R1_ILLEGAL_COMMAND (1 << 22)
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#define R1_APP_CMD (1 << 5)
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#define MMC_RSP_PRESENT (1 << 0)
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
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#define MMC_RSP_MASK (0xF)
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#define MMC_RSP_NONE (0)
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#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
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#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
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#define MMC_RSP_R3 (MMC_RSP_PRESENT)
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#define MMC_RSP_R4 (MMC_RSP_PRESENT)
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#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
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#define MMC_CMD_MASK (3 << 4)
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#define MMC_CMD_AC (0 << 4)
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#define MMC_CMD_ADTC (1 << 4)
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#define MMC_CMD_BC (2 << 4)
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#define MMC_CMD_BCR (3 << 4)
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#define MMCPART_NOAVAILABLE (0xff)
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#define PART_ACCESS_MASK (0x7)
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#define PART_SUPPORT (0x1)
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#define PART_BOOT_PART_MASK (0x7 << 3)
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#define PART_BOOT_PART_NONE (0x0)
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#define PART_BOOT_PART_1 (0x1)
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#define PART_BOOT_PART_2 (0x2)
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#define PART_BOOT_USER (0x7)
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#define PART_BOOT_ACK_MASK (0x1 << 6)
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#define PART_BOOT_ACK_ENB (0x1)
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#define MMCBOOT_BUS_NOAVAILABLE (0xff)
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#define BOOT_MODE_MASK (0x3 << 3)
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#define BOOT_SDR_NORMAL (0x0)
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#define BOOT_SDR_HS (0x1)
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#define BOOT_DDR (0x2)
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#define BOOT_RST_BUS_COND_MASK (0x1 << 2)
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#define BOOT_RST_BUS_COND (0x0)
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#define BOOT_RETAIN_BUS_COND (0x1)
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#define BOOT_BUS_WIDTH_MASK (0x3 << 0)
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#define BOOT_BUS_SDRx1_DDRx4 (0x0)
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#define BOOT_BUS_SDRx4_DDRx4 (0x1)
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#define BOOT_BUS_SDRx8_DDRx8 (0x2)
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#define MMC_TYPE_SD_CARD (1)
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#define MMC_TYPE_EMMC_UDA (2)
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#define MMC_TYPE_EMMC_BOOT (3)
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#define MMC_BLOCK_SIZE 512
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s32 mmc_init(int id);
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s32 mmc_deinit(int id);
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s32 mmc_switch_part(struct aic_sdmc *host, u32 part_num);
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u32 mmc_bread(void *priv, u32 start, u32 blkcnt, u8 *dst);
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u32 mmc_bwrite(struct aic_sdmc *host, u32 start, u32 blkcnt, const u8 *src);
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u32 mmc_berase(struct aic_sdmc *host, u32 start, u32 blkcnt);
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struct aic_sdmc *find_mmc_dev_by_index(int id);
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struct aic_partition *mmc_new_partition(char *s, u64 start);
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void mmc_free_partition(struct aic_partition *part);
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struct aic_partition *mmc_create_gpt_part(void);
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void sdcard_hotplug_init(void);
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void sdcard_hotplug_act(void);
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int mmc_block_init(struct aic_sdmc *host);
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int mmc_block_refresh(struct aic_sdmc *host);
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int mmc_block_deinit(struct aic_sdmc *host);
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int mmc_rpmb_get_counter(struct aic_sdmc *host, unsigned long *pcounter);
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int mmc_rpmb_set_key(struct aic_sdmc *host, void *key);
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int mmc_rpmb_read(struct aic_sdmc *host, void *addr, unsigned short blk,
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unsigned short cnt, unsigned char *key);
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int mmc_rpmb_write(struct aic_sdmc *host, void *addr, unsigned short blk,
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unsigned short cnt, unsigned char *key);
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int mmc_rpmb_route_frames(struct aic_sdmc *host, void *req, unsigned long reqlen,
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void *rsp, unsigned long rsplen);
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#endif /* _AIC_MMC_H_ */
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