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286 lines
8.6 KiB
C
286 lines
8.6 KiB
C
/*
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* Copyright (c) 2023-2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: dwj <weijie.ding@artinchip.com>
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*/
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#ifndef _AIC_HAL_CAN_H_
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#define _AIC_HAL_CAN_H_
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#include <aic_core.h>
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/* Register address */
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#define CAN_MODE_REG 0x0000
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#define CAN_MCR_REG 0x0004
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#define CAN_STAT_REG 0x0008
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#define CAN_INTR_REG 0x000C
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#define CAN_INTEN_REG 0x0010
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#define CAN_BTR0_REG 0x0018
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#define CAN_BTR1_REG 0x001C
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#define CAN_ARBLOST_REG 0x002C
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#define CAN_ERRCODE_REG 0x0030
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#define CAN_ERRWT_REG 0x0034
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#define CAN_RXERR_REG 0x0038
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#define CAN_TXERR_REG 0x003C
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#define CAN_BUF0_REG 0x0040
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#define CAN_BUF1_REG 0x0044
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#define CAN_BUF2_REG 0x0048
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#define CAN_BUF3_REG 0x004C
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#define CAN_BUF4_REG 0x0050
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#define CAN_BUF5_REG 0x0054
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#define CAN_RXCODE0_REG 0x0040
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#define CAN_RXCODE1_REG 0x0044
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#define CAN_RXCODE2_REG 0x0048
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#define CAN_RXCODE3_REG 0x004C
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#define CAN_RXMASK0_REG 0x0050
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#define CAN_RXMASK1_REG 0x0054
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#define CAN_RXMASK2_REG 0x0058
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#define CAN_RXMASK3_REG 0x005C
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#define CAN_RXC_REG 0x0074
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#define CAN_RSADDR_REG 0x0078
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#define CAN_RXFIFO_REG 0x0080
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#define CAN_TXBRO_REG 0x0180
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#define CAN_VERSION_REG 0x0FFC
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/* Register bit filed */
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/* Mode register */
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#define CAN_MODE_SLEEP BIT(4)
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#define CAN_MODE_WAKEUP (0 << 4)
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#define CAN_MODE_FILTER_SINGLE BIT(3)
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#define CAN_MODE_FILTER_DUAL (0 << 3)
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#define CAN_MODE_SELFTEST BIT(2)
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#define CAN_MODE_LISTEN BIT(1)
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#define CAN_MODE_RST BIT(0)
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#define CAN_MODE_NORMAL 0
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#define CAN_MODE_MASK 0x17
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/* Control reg, write only */
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#define CAN_MCR_SELFREQ BIT(4)
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#define CAN_MCR_CLR_OVF BIT(3)
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#define CAN_MCR_RXB_REL BIT(2)
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#define CAN_MCR_ABORTREQ BIT(1)
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#define CAN_MCR_TXREQ BIT(0)
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/* Status reg, read only */
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#define CAN_STAT_BUS BIT(7)
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#define CAN_STAT_ERR BIT(6)
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#define CAN_STAT_TX BIT(5)
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#define CAN_STAT_RX BIT(4)
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#define CAN_STAT_TXC BIT(3)
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#define CAN_STAT_TXB BIT(2)
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#define CAN_STAT_OVF BIT(1)
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#define CAN_STAT_RXB BIT(0)
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/* interrupt flag reg */
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#define CAN_INTR_ERRB BIT(7)
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#define CAN_INTR_ARBLOST BIT(6)
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#define CAN_INTR_ERRP BIT(5)
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#define CAN_INTR_WAKEUP BIT(4)
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#define CAN_INTR_OVF BIT(3)
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#define CAN_INTR_ERRW BIT(2)
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#define CAN_INTR_TX BIT(1)
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#define CAN_INTR_RX BIT(0)
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/* interrupt enable reg */
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#define CAN_INTEN_ERRB BIT(7)
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#define CAN_INTEN_ARBLOST BIT(6)
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#define CAN_INTEN_ERRP BIT(5)
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#define CAN_INTEN_WAKEUP BIT(4)
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#define CAN_INTEN_OVF BIT(3)
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#define CAN_INTEN_ERRW BIT(2)
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#define CAN_INTEN_TXI BIT(1)
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#define CAN_INTEN_RXI BIT(0)
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/* btr0 reg */
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#define CAN_BTR0_SJW_MASK GENMASK(7, 6)
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#define CAN_BTR0_BRP_MASK (0x3F)
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/* btr1 reg */
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#define CAN_BTR1_SAM_MASK BIT(7)
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#define CAN_BTR1_TS2_MASK GENMASK(6, 4)
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#define CAN_BTR1_TS1_MASK (0xF)
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/* arb lost reg */
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#define CAN_ARBLOST_CAP_MASK (0x1F)
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/* error code reg */
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#define CAN_ERRCODE_ERRTYPE_MASK GENMASK(7, 6)
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#define CAN_ERRCODE_ERRTYPE_BIT (0x0 << 6)
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#define CAN_ERRCODE_ERRTYPE_FORMAT (0x1 << 6)
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#define CAN_ERRCODE_ERRTYPE_STUFF (0x2 << 6)
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#define CAN_ERRCODE_ERRTYPE_OTHER (0x3 << 6)
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#define CAN_ERRCODE_DIR BIT(5)
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#define CAN_ERRCODE_SEGCODE_MASK (0x1f)
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#define CAN_ERRCODE_ACK_SLOT (0x19)
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/* buf0 reg */
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#define CAN_BUF0_MSG_EFF_FLAG BIT(7)
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#define CAN_BUF0_MSG_RTR_FLAG BIT(6)
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#define CAN_BUF0_MSG_EFF_SHIFT 7
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#define CAN_BUF0_MSG_RTR_SHIFT 6
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#define CAN_TSEG_MIN 7
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#define CAN_ERRP_THRESHOLD 127
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#define CAN_BUS_ERRCODE_CRCERRCNT 13
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#define CAN_BUS_ERRCODE_ACKERRCNT 15
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typedef enum {
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ACTIVE_STATUS,
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WARNING_STATUS,
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PASSIVE_STATUS,
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BUS_OFF = 4,
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} can_state_t;
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struct can_bittiming_const {
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u32 sync_seg;
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u32 tseg1_min;
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u32 tseg1_max;
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u32 tseg2_min;
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u32 tseg2_max;
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u32 sjw_max;
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u32 brp_min;
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u32 brp_max;
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u32 brp_inc;
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};
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typedef enum {
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CAN_NORMAL_MODE = 0,
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CAN_RESET_MODE = BIT(0),
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CAN_LISTEN_MODE = BIT(1),
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CAN_SELFTEST_MODE = BIT(2),
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CAN_SLEEP_MODE = BIT(4),
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} can_mode_t;
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enum {
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CAN_FRAME_TYPE_DATA = 0,
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CAN_FRAME_TYPE_REMOTE = 1,
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};
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typedef enum {
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TX_REQ = BIT(0),
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ABORT_REQ = BIT(1),
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RXB_REL_REQ = BIT(2),
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CLR_OF_REQ = BIT(3),
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SELF_REQ = BIT(4),
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} can_op_req_t;
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typedef struct {
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u8 code;
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char *msg;
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} bus_err_msg_t;
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typedef struct can_status {
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can_state_t current_state;
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u32 recverrcnt;
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u32 snderrcnt;
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u32 rxovercnt;
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u32 arblostcnt;
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u32 biterrcnt;
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u32 formaterrcnt;
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u32 stufferrcnt;
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u32 othererrcnt;
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u32 recvpkgcnt;
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u32 sndpkgcnt;
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u32 ackerrcnt;
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u32 crcerrcnt;
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u32 rxerr;
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u32 txerr;
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} can_status_t;
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typedef struct {
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u32 id;
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u8 rtr;
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u8 ide;
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u8 dlc;
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u8 data[8];
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} can_msg_t;
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typedef struct can_handle can_handle;
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struct can_handle {
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unsigned long can_base;
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u32 irq_num;
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u32 clk_id;
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u32 idx;
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void (*callback)(can_handle * phandle, void *arg);
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void *arg;
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u32 baudrate;
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can_msg_t msg;
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can_status_t status;
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unsigned long mode;
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};
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typedef enum {
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FILTER_CLOSE = 0,
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SINGLE_FILTER_MODE = 1,
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DUAL_FILTER_MODE = 2,
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} can_filter_mode_t;
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typedef union {
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struct single_filter_std {
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u16 id_filter;
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u8 rtr_filter;
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u8 data0_filter;
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u8 data1_filter;
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} sfs;
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struct single_filter_ext {
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u32 id_filter;
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u8 rtr_filter;
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} sfe;
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struct dual_filter_std {
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u16 id_filter0;
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u8 rtr_filter0;
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u8 data0_filter0;
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u16 id_filter1;
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u8 rtr_filter1;
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} dfs;
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struct dual_filter_ext {
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u16 id_filter0;
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u16 id_filter1;
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} dfe;
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} can_filter_t;
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typedef struct can_filter_config {
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can_filter_mode_t filter_mode;
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/* is_eff indicates whether the filter is used to filter extended frame */
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u8 is_eff;
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can_filter_t rxcode;
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can_filter_t rxmask;
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} can_filter_config_t;
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static inline void hal_can_enable_interrupt(can_handle *phandle)
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{
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writel(0xFF, phandle->can_base + CAN_INTEN_REG);
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}
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static inline void hal_can_disable_interrupt(can_handle *phandle)
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{
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writel(0, phandle->can_base + CAN_INTEN_REG);
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}
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#define CAN_IOCTL_SET_MODE 1
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#define CAN_IOCTL_SET_FILTER 2
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#define CAN_IOCTL_SET_BAUDRATE 4
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#define CAN_IOCTL_GET_BAUDRATE 8
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#define CAN_IOCTL_RELEASE_MODE 0x10
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#define CAN_EVENT_RX_IND 0x01 /* Rx indication */
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#define CAN_EVENT_TX_DONE 0x02 /* Tx complete */
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#define CAN_EVENT_TX_FAIL 0x03 /* Tx fail */
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#define CAN_EVENT_RXOF_IND 0x06 /* Rx overflow */
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int hal_can_init(can_handle *phandle, u32 can_idx);
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void hal_can_uninit(can_handle *phandle);
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void hal_can_send_frame(can_handle *phandle, can_msg_t * msg, can_op_req_t req);
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void hal_can_receive_frame(can_handle *phandle, can_msg_t * msg);
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int hal_can_ioctl(can_handle *phandle, int cmd, void *arg);
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int hal_can_attach_callback(can_handle *phandle, void *callback, void *arg);
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void hal_can_detach_callback(can_handle *phandle);
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irqreturn_t hal_can_isr_handler(int irq_num, void *arg);
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#endif
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