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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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332 lines
12 KiB
C
332 lines
12 KiB
C
/*
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* Copyright (c) 2023, Artinchip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MIPI_DSI_REG_V1_0_H_
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#define _MIPI_DSI_REG_V1_0_H_
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#include <aic_core.h>
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#include <artinchip_fb.h>
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#include "aic_hal_disp_reg_util.h"
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enum dsi_mode {
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DSI_MOD_VID_PULSE = BIT(0),
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DSI_MOD_VID_EVENT = BIT(1),
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DSI_MOD_VID_BURST = BIT(2),
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DSI_MOD_CMD_MODE = BIT(3),
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DSI_CLOCK_NON_CONTINUOUS = BIT(4),
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};
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enum dsi_format {
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DSI_FMT_RGB888 = 0,
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DSI_FMT_RGB666L = 1,
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DSI_FMT_RGB666 = 2,
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DSI_FMT_RGB565 = 3,
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DSI_FMT_MAX
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};
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#define DSI_MAX_LANE_NUM 4
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#define DSI_CTL_PKG_CFG_CRC_RX_EN BIT(7)
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#define DSI_CTL_PKG_CFG_ECC_RX_EN BIT(6)
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#define DSI_CTL_PKG_CFG_BTA_EN BIT(5)
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#define DSI_CTL_PKG_CFG_EOTP_RX_EN BIT(4)
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#define DSI_CTL_PKG_CFG_EOTP_TX_EN BIT(3)
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#define DSI_CTL_DSI_MODE BIT(1)
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#define DSI_CTL_EN BIT(0)
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#define DSI_CLK_CFG_TO_DIV_MASK GENMASK(15, 8)
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#define DSI_CLK_CFG_TO_DIV(x) (((x) & 0xFF) << 8)
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#define DSI_CLK_CFG_LP_DIV_MASK GENMASK(7, 0)
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#define DSI_CLK_CFG_LP_DIV(x) (((x) & 0xFF) << 0)
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#define DSI_DPI_VC_NUM_MASK GENMASK(1, 0)
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#define DSI_DPI_VC_NUM(x) (((x) & 0x3) << 0)
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#define DSI_DPI_IN_FMT_LOOSELY18 BIT(8)
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#define DSI_DPI_IN_FMT_DT_MASK GENMASK(3, 0)
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#define DSI_DPI_IN_FMT_DT(x) (((x) & 0xF) << 0)
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#define DSI_DPI_IN_POL_COLORM BIT(4)
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#define DSI_DPI_IN_POL_SHUTDOWN BIT(3)
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#define DSI_DPI_IN_POL_HSYNC BIT(2)
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#define DSI_DPI_IN_POL_VSYNC BIT(1)
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#define DSI_DPI_IN_POL_DE BIT(0)
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#define DSI_POL_HIGH_ACTIVE 0
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#define DSI_POL_LOW_ACTIVE 1
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#define DSI_DPI_LPTX_TIME_OUTVACT_MASK GENMASK(24, 16)
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#define DSI_DPI_LPTX_TIME_OUTVACT(x) (((x) & 0xFF) << 16)
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#define DSI_DPI_LPTX_TIME_INVACT_MASK GENMASK(7, 0)
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#define DSI_DPI_LPTX_TIME_INVACT(x) (((x) & 0xFF) << 0)
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#define DSI_VID_MODE_CFG_TEST_DIR BIT(24)
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#define DSI_VID_MODE_CFG_TEST_MODE BIT(20)
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#define DSI_VID_MODE_CFG_TEST_EN BIT(16)
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#define DSI_VID_MODE_CFG_CMD_LPTX_FORCE BIT(15)
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#define DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN BIT(14)
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#define DSI_VID_MODE_CFG_LP_EN_HFP BIT(13)
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#define DSI_VID_MODE_CFG_LP_EN_HBP BIT(12)
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#define DSI_VID_MODE_CFG_LP_EN_VACT BIT(11)
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#define DSI_VID_MODE_CFG_LP_EN_VFP BIT(10)
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#define DSI_VID_MODE_CFG_LP_EN_VBP BIT(9)
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#define DSI_VID_MODE_CFG_LP_EN_VSA BIT(8)
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#define DSI_VID_MODE_CFG_TYPE_MASK GENMASK(1, 0)
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#define DSI_VID_MODE_CFG_TYPE(x) ((((x) >> 1) & 0x3) << 0)
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#define DSI_VID_HBP_TIME_MASK GENMASK(27, 16)
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#define DSI_VID_HBP_TIME(x) (((x) & 0xFFF) << 16)
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#define DSI_VID_HSA_TIME_MASK GENMASK(11, 0)
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#define DSI_VID_HSA_TIME(x) (((x) & 0xFFF) << 0)
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#define DSI_VID_VFP_LINE_MASK GENMASK(25, 16)
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#define DSI_VID_VFP_LINE(x) (((x) & 0x3FF) << 16)
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#define DSI_VID_VBP_TIME_MASK GENMASK(9, 0)
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#define DSI_VID_VBP_TIME(x) (((x) & 0x3FF) << 0)
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#define DSI_VID_VSA_LINE_MASK GENMASK(25, 16)
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#define DSI_VID_VSA_LINE(x) (((x) & 0x3FF) << 16)
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#define DSI_VID_VACT_TIME_MASK GENMASK(13, 0)
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#define DSI_VID_VACT_TIME(x) (((x) & 0x3FFF) << 0)
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#define DSI_CMD_MODE_CFG_PKG_TX_HS 0
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#define DSI_CMD_MODE_CFG_PKG_TX_LP 1
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#define DSI_CMD_MODE_CFG_MAX_RD_PKG_SIZE BIT(24)
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#define DSI_CMD_MODE_CFG_DCS_LW BIT(19)
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#define DSI_CMD_MODE_CFG_DCS_SR_0P BIT(18)
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#define DSI_CMD_MODE_CFG_DCS_SW_1P BIT(17)
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#define DSI_CMD_MODE_CFG_DCS_SW_0P BIT(16)
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#define DSI_CMD_MODE_CFG_GEN_LW BIT(14)
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#define DSI_CMD_MODE_CFG_GEN_SR_2P BIT(13)
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#define DSI_CMD_MODE_CFG_GEN_SR_1P BIT(12)
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#define DSI_CMD_MODE_CFG_GEN_SR_0P BIT(11)
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#define DSI_CMD_MODE_CFG_GEN_SW_2P BIT(10)
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#define DSI_CMD_MODE_CFG_GEN_SW_1P BIT(9)
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#define DSI_CMD_MODE_CFG_GEN_SW_0P BIT(8)
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#define DSI_CMD_MODE_CFG_ACK_REQ_EN BIT(1)
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#define DSI_CMD_MODE_CFG_TE_EN BIT(0)
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#define DSI_CMD_PKG_STA_RD_CMD_BUSY BIT(6)
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#define DSI_CMD_PKG_STA_PLD_R_FULL BIT(5)
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#define DSI_CMD_PKG_STA_PLD_R_EMPTY BIT(4)
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#define DSI_CMD_PKG_STA_PLD_W_FULL BIT(3)
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#define DSI_CMD_PKG_STA_PLD_W_EMPTY_SHIFT 2
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#define DSI_CMD_PKG_STA_PLD_W_EMPTY BIT(2)
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#define DSI_CMD_PKG_STA_CMD_FULL BIT(1)
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#define DSI_CMD_PKG_STA_CMD_EMPTY BIT(0)
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#define DSI_TO_CNT_CFG_HSTX_MASK GENMASK(31, 16)
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#define DSI_TO_CNT_CFG_HSTX(x) (((x) & 0x3FF) << 16)
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#define DSI_TO_CNT_CFG_LPRX_MASK GENMASK(15, 0)
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#define DSI_TO_CNT_CFG_LPRX(x) (((x) & 0x3FF) << 0)
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#define DSI_PHY_CLK_TIME_HS2LP_MASK GENMASK(25, 16)
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#define DSI_PHY_CLK_TIME_HS2LP(x) (((x) & 0x1FF) << 16)
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#define DSI_PHY_CLK_TIME_LP2HS_MASK GENMASK(9, 0)
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#define DSI_PHY_CLK_TIME_LP2HS(x) (((x) & 0x1FF) << 0)
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#define DSI_PHY_DATA_TIME_HS2LP_MASK GENMASK(25, 16)
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#define DSI_PHY_DATA_TIME_HS2LP(x) (((x) & 0x1FF) << 16)
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#define DSI_PHY_DATA_TIME_LP2HS_MASK GENMASK(9, 0)
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#define DSI_PHY_DATA_TIME_LP2HS(x) (((x) & 0x1FF) << 0)
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#define DSI_PHY_CFG_RST_PLL_FORCE BIT(7)
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#define DSI_PHY_CFG_RST_CLK_EN BIT(6)
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#define DSI_PHY_CFG_RST_RSTN BIT(5)
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#define DSI_PHY_CFG_RST_SHUTDOWNZ BIT(4)
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#define DSI_PHY_CFG_AUTO_CLK_EN BIT(3)
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#define DSI_PHY_CFG_HSCLK_REQ BIT(2)
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#define DSI_PHY_CFG_LP11_TIME_SHIFT 8
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#define DSI_PHY_CFG_LP11_TIME_MASK GENMASK(15, 8)
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#define DSI_PHY_CFG_LP11_TIME(x) (((x) & 0xFF) << 8)
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#define DSI_PHY_CFG_DATA_LANE_MASK GENMASK(1, 0)
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#define DSI_PHY_CFG_DATA_LANE(x) (((x) & 0x3) << 0)
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#define DSI_PHY_STA_ULPS_ACTIVE_NOT_4 BIT(12)
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#define DSI_PHY_STA_STOP_STATE_3 BIT(11)
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#define DSI_PHY_STA_ULPS_ACTIVE_NOT_2 BIT(10)
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#define DSI_PHY_STA_STOP_STATE_2 BIT(9)
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#define DSI_PHY_STA_ULPS_ACTIVE_NOT_1 BIT(8)
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#define DSI_PHY_STA_STOP_STATE_1 BIT(7)
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#define DSI_PHY_STA_RXULPS_ESC_0 BIT(6)
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#define DSI_PHY_STA_ULPS_ACTIVE_NOT_0 BIT(5)
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#define DSI_PHY_STA_STOP_STATE_0_SHIFT 4
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#define DSI_PHY_STA_STOP_STATE_0 BIT(4)
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#define DSI_PHY_STA_ULPS_ACTIVE_NOT_C BIT(3)
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#define DSI_PHY_STA_STOP_STATE_C_SHIFT 2
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#define DSI_PHY_STA_STOP_STATE_C BIT(2)
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#define DSI_PHY_STA_PHY_DIRECTION BIT(1)
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#define DSI_PHY_STA_PHY_LOCK BIT(0)
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#define DSI_PHY_TEST1_CLK BIT(1)
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#define DSI_PHY_TEST1_CLR BIT(0)
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#define DSI_PHY_TEST2_EN BIT(16)
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#define DSI_PHY_TEST2_DOUT_MASK GENMASK(15, 8)
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#define DSI_PHY_TEST2_DOUT(x) (((x) & 0xFF) << 8)
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#define DSI_PHY_TEST2_DIN_MASK GENMASK(7, 0)
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#define DSI_PHY_TEST2_DIN(x) (((x) & 0xFF) << 0)
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#define DSI_DPI_IF_CFG_COLORM BIT(3)
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#define DSI_DPI_IF_CFG_SHUTD BIT(2)
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#define DSI_DPI_IF_CFG_FMT_MASK GENMASK(1, 0)
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#define DSI_DPI_IF_CFG_FMT(x) (((x) & 0x3) << 0)
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#define DSI_ANA_CFG2_EN_CLK BIT(12)
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#define DSI_ANA_CFG2_RCAL_SHIFT 10
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#define DSI_ANA_CFG2_RCAL_FLAG BIT(10)
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#define DSI_ANA_CFG2_ON_RESCAL BIT(9)
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#define DSI_ANA_CFG2_EN_RESCAL BIT(8)
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#define DSI_ANA_CFG2_EN_LDO_MASK GENMASK(7, 3)
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#define DSI_ANA_CFG2_EN_LDO(x) (((x) & 0x1F) << 3)
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#define DSI_ANA_CFG2_EN_VP_MASK GENMASK(2, 1)
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#define DSI_ANA_CFG2_EN_VP(x) (((x) & 0x3) << 1)
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#define DSI_ANA_CFG2_EN_BIAS BIT(0)
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#define DSI_DATA_LANE_POL_MASK GENMASK(19, 16)
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#define DSI_DATA_LANE_POL(x) (((x) & 0xF) << 16)
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#define DSI_DATA_CLK_POL BIT(15)
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/* The register of MIPI DSI controller */
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#define DSI_CTL 0x00
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#define DSI_CLK_CFG 0x04
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#define DSI_DPI_IN_POL 0x10
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#define DSI_DPI_IN_FMT 0x14
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#define DSI_DPI_VC 0x18
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#define DSI_DPI_LPTX_TIME 0x1C
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#define DSI_GEN_PH_CFG 0x20
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#define DSI_GEN_PD_CFG 0x24
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#define DSI_GEN_VC_RX 0x28
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#define DSI_VID_MODE_CFG 0x30
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#define DSI_VID_PKG_SIZE 0x34
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#define DSI_VID_CHK_NUM 0x38
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#define DSI_VID_NULL_SIZE 0x3C
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#define DSI_VID_HINACT_TIME 0x40
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#define DSI_VID_HT_TIME 0x44
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#define DSI_VID_VBLANK_LINE 0x48
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#define DSI_VID_VACT_LINE 0x4C
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#define DSI_CMD_MODE_CFG 0x50
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#define DSI_EDPI_CMD_SIZE 0x54
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#define DSI_CMD_PKG_STA 0x58
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#define DSI_IRQ_EN1 0x60
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#define DSI_IRQ_EN2 0x64
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#define DSI_IRQ_STA1 0x68
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#define DSI_IRQ_STA2 0x6C
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#define DSI_TO_CNT_CFG 0x70
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#define DSI_TO_RD 0x74
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#define DSI_TO_WR 0x78
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#define DSI_TO_BTA 0x7C
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#define DSI_PHY_CFG 0x80
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#define DSI_PHY_STA 0x84
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#define DSI_PHY_CLK_TIME 0x88
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#define DSI_PHY_DATA_TIME 0x8C
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#define DSI_PHY_RD_TIME 0x90
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#define DSI_PHY_TEST1 0xC0
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#define DSI_PHY_TEST2 0xC4
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#define DSI_DPI_IF_CFG 0x400
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#define DSI_LANE_CFG 0x410
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#define DSI_ANA_CFG1 0x500
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#define DSI_ANA_CFG2 0x504
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#define DSI_ANA_CFG3 0x508
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#define DSI_ANA_CFG4 0x50C
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/* Processor to Peripheral Direction (Processor-Sourced) Packet Data Types */
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#define DSI_DT_VSS 0x01
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#define DSI_DT_VSE 0x11
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#define DSI_DT_HSS 0x21
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#define DSI_DT_HSE 0x31
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#define DSI_DT_EOT 0x08
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#define DSI_DT_CM_OFF 0x02
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#define DSI_DT_CM_ON 0x12
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#define DSI_DT_SHUT_DOWN 0x22
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#define DSI_DT_TURN_ON 0x32
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#define DSI_DT_GEN_WR_P0 0x03
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#define DSI_DT_GEN_WR_P1 0x13
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#define DSI_DT_GEN_WR_P2 0x23
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#define DSI_DT_GEN_RD_P0 0x04
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#define DSI_DT_GEN_RD_P1 0x14
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#define DSI_DT_GEN_RD_P2 0x24
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#define DSI_DT_DCS_WR_P0 0x05
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#define DSI_DT_DCS_WR_P1 0x15
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#define DSI_DT_DCS_RD_P0 0x06
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#define DSI_DT_MAX_RET_SIZE 0x37
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#define DSI_DT_NULL 0x09
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#define DSI_DT_BLK 0x19
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#define DSI_DT_GEN_LONG_WR 0x29
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#define DSI_DT_DCS_LONG_WR 0x39
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#define DSI_DT_PIXEL_RGB565 0x0E
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#define DSI_DT_PIXEL_RGB666P 0x1E
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#define DSI_DT_PIXEL_RGB666 0x2E
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#define DSI_DT_PIXEL_RGB888 0x3E
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/* Data Types for Peripheral-sourced Packets */
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#define DSI_DT_ACK_ERR 0x02
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#define DSI_DT_EOT_PERI 0x08
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#define DSI_DT_GEN_RD_R1 0x11
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#define DSI_DT_GEN_RD_R2 0x12
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#define DSI_DT_GEN_LONG_RD_R 0x1A
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#define DSI_DT_DCS_LONG_RD_R 0x1C
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#define DSI_DT_DCS_RD_R1 0x21
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#define DSI_DT_DCS_RD_R2 0x22
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#define DSI_DCS_ENTER_IDLE_MODE 0x39
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#define DSI_DCS_ENTER_INVERT_MODE 0x21
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#define DSI_DCS_ENTER_NORMAL_MODE 0x13
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#define DSI_DCS_ENTER_PARTIAL_MODE 0x12
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#define DSI_DCS_ENTER_SLEEP_MODE 0x10
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#define DSI_DCS_EXIT_IDLE_MODE 0x38
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#define DSI_DCS_EXIT_INVERT_MODE 0x20
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#define DSI_DCS_EXIT_SLEEP_MODE 0x11
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#define DSI_DCS_GET_ADDRESS_MODE 0x0b
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#define DSI_DCS_GET_BLUE_CHANNEL 0x08
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#define DSI_DCS_GET_DIAGNOSTIC_RESULT 0x0f
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#define DSI_DCS_GET_DISPLAY_MODE 0x0d
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#define DSI_DCS_GET_GREEN_CHANNEL 0x07
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#define DSI_DCS_GET_PIXEL_FORMAT 0x0c
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#define DSI_DCS_GET_POWER_MODE 0x0a
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#define DSI_DCS_GET_RED_CHANNEL 0x06
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#define DSI_DCS_GET_SCANLINE 0x45
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#define DSI_DCS_GET_SIGNAL_MODE 0x0e
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#define DSI_DCS_NOP 0x00
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#define DSI_DCS_READ_DDB_CONTINUE 0xa8
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#define DSI_DCS_READ_DDB_START 0xa1
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#define DSI_DCS_READ_MEMORY_CONTINUE 0x3e
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#define DSI_DCS_READ_MEMORY_START 0x2e
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#define DSI_DCS_SET_ADDRESS_MODE 0x36
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#define DSI_DCS_SET_COLUMN_ADDRESS 0x2a
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#define DSI_DCS_SET_DISPLAY_OFF 0x28
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#define DSI_DCS_SET_DISPLAY_ON 0x29
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#define DSI_DCS_SET_GAMMA_CURVE 0x26
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#define DSI_DCS_SET_PAGE_ADDRESS 0x2b
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#define DSI_DCS_SET_PARTIAL_AREA 0x30
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#define DSI_DCS_SET_PIXEL_FORMAT 0x3a
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#define DSI_DCS_SET_SCROLL_AREA 0x33
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#define DSI_DCS_SET_SCROLL_START 0x37
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#define DSI_DCS_SET_TEAR_OFF 0x34
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#define DSI_DCS_SET_TEAR_ON 0x35
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#define DSI_DCS_SET_TEAR_SCANLINE 0x44
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#define DSI_DCS_SOFT_RESET 0x01
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#define DSI_DCS_WRITE_LUT 0x2d
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#define DSI_DCS_WRITE_MEMORY_CONTINUE 0x3c
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#define DSI_DCS_WRITE_MEMORY_START 0x2c
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void dsi_set_lane_assign(void *base, u32 ln_assign);
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void dsi_set_lane_polrs(void *base, u32 ln_polrs);
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void dsi_set_data_clk_polrs(void *base, u32 dc_inv);
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void dsi_set_clk_div(void *base, ulong mclk, ulong lp_rate);
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void dsi_pkg_init(void *base);
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void dsi_phy_init(void *base, ulong mclk, u32 lane, enum dsi_mode mode);
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void dsi_hs_clk(void *base, u32 enable);
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void dsi_set_vm(void *base, enum dsi_mode mode, enum dsi_format format,
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u32 lane, u32 vc, const struct display_timing *timing);
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void dsi_cmd_wr(void *base, u32 dt, u32 vc, const u8 *data, u32 len);
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void dsi_dcs_lw(void *base, u32 enable);
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#endif // end of _MIPI_DSI_REG_V1_0_H_
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