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110 lines
2.2 KiB
C
110 lines
2.2 KiB
C
/*
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* Copyright (c) 2023, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: Mingfeng.Li <mingfeng.li@artinchip.com>
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*/
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#ifndef _AIC_HAL_AXICFG_
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#define _AIC_HAL_AXICFG_
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#include <aic_common.h>
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#include <stdbool.h>
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#include <rtconfig.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define HAL_AXICFG_CPU_P_NUM 0
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#define HAL_AXICFG_AHB_P_NUM 1
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#define HAL_AXICFG_DE_P_NUM 2
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#define HAL_AXICFG_GE_P_NUM 3
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#define HAL_AXICFG_VE_P_NUM 4
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#define HAL_AXICFG_DVP_P_NUM 5
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#define HAL_AXICFG_CE_P_NUM 6
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#define HAL_AXICFG_W_READ 0
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#define HAL_AXICFG_W_WRITE 1
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#define HAL_AXICFG_EXT_QOS 0 //QOS set by main device
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#define HAL_AXICFG_INT_QOS 1 //QOS set by QOS_VAL reg
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#define HAL_AXICFG_BASE 0x184FE000
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typedef enum hal_axicfg_port_e {
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HAL_AXICFG_PORT_CPU = 0,
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HAL_AXICFG_PORT_AHB = 1,
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HAL_AXICFG_PORT_DE = 2,
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HAL_AXICFG_PORT_GE = 3,
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HAL_AXICFG_PORT_VE = 4,
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HAL_AXICFG_PORT_DVP = 5,
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HAL_AXICFG_PORT_MDI = 5,
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HAL_AXICFG_PORT_CE = 6,
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HAL_AXICFG_PORT_MAX
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} hal_axicfg_port_t;
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#ifndef AIC_AXICFG_PORT_CPU_EN
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#define AXICFG_CPU_EN 0
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#define AIC_AXICFG_PORT_CPU_PRIO 0
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#else
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#define AXICFG_CPU_EN 1
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#endif
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#ifndef AIC_AXICFG_PORT_AHB_EN
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#define AXICFG_AHB_EN 0
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#define AIC_AXICFG_PORT_AHB_PRIO 0
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#else
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#define AXICFG_AHB_EN 1
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#endif
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#ifndef AIC_AXICFG_PORT_DE_EN
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#define AXICFG_DE_EN 0
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#define AIC_AXICFG_PORT_DE_PRIO 0
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#else
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#define AXICFG_DE_EN 1
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#endif
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#ifndef AIC_AXICFG_PORT_GE_EN
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#define AXICFG_GE_EN 0
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#define AIC_AXICFG_PORT_GE_PRIO 0
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#else
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#define AXICFG_GE_EN 1
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#endif
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#ifndef AIC_AXICFG_PORT_VE_EN
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#define AXICFG_VE_EN 0
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#define AIC_AXICFG_PORT_VE_PRIO 0
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#else
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#define AXICFG_VE_EN 1
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#endif
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#ifndef AIC_AXICFG_PORT_DVP_EN
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#define AXICFG_DVP_EN 0
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#define AIC_AXICFG_PORT_DVP_PRIO 0
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#else
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#define AXICFG_DVP_EN 1
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#endif
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#ifndef AIC_AXICFG_PORT_CE_EN
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#define AXICFG_CE_EN 0
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#define AIC_AXICFG_PORT_CE_PRIO 0
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#else
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#define AXICFG_CE_EN 1
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#endif
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struct hal_axicfg_table {
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u8 enable;
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u8 priority;
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};
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// read: mode = 0; write: mode = 1;
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int hal_axicfg_module_wr_init(u8 mode, hal_axicfg_port_t device_p, u8 priority);
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int hal_axicfg_module_init(hal_axicfg_port_t device_p, u8 priority);
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#ifdef __cplusplus
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}
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#endif
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#endif
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