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128 lines
4.9 KiB
C
128 lines
4.9 KiB
C
/*
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* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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* Authors: dwj <weijie.ding@artinchip.com>
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*/
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#ifndef _HAL_CIR_H_
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#define _HAL_CIR_H_
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#include <aic_core.h>
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#define AIC_IR_DEV "aic-ir"
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#define DEFAULT_FREQ 38000
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/* Register definition */
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#define CIR_MCR_REG 0x00
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#define CIR_MCR_TXFIFO_CLR BIT(17)
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#define CIR_MCR_RXFIFO_CLR BIT(16)
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#define CIR_MCR_TX_STOP BIT(9)
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#define CIR_MCR_TX_START BIT(8)
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#define CIR_MCR_TX_EN BIT(1)
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#define CIR_MCR_RX_EN BIT(0)
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#define CIR_INTR_REG 0x04
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#define CIR_INTR_TXB_AVL_INT BIT(6)
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#define CIR_INTR_TXEND_INT BIT(5)
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#define CIR_INTR_TX_UNF_INT BIT(4)
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#define CIR_INTR_RXB_AVL_INT BIT(2)
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#define CIR_INTR_RX_END_INT BIT(1)
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#define CIR_INTR_RX_OVF_INT BIT(0)
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#define CIR_INTEN_REG 0x08
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#define CIR_INTEN_TXB_EMPTY_LEVEL_POS (16)
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#define CIR_INTEN_TXB_EMPTY_LEVEL(x) ((x) << CIR_INTEN_TXB_EMPTY_LEVEL_POS)
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#define CIR_INTEN_RXB_AVL_LEVEL_POS (8)
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#define CIR_INTEN_RXB_AVL_LEVEL(x) ((x) << CIR_INTEN_RXB_AVL_LEVEL_POS)
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#define CIR_INTEN_TXB_AVL_EN BIT(6)
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#define CIR_INTEN_TXEND_EN BIT(5)
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#define CIR_INTEN_TX_UNF_EN BIT(4)
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#define CIR_INTEN_RXB_AVL_EN BIT(2)
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#define CIR_INTEN_RXEND_EN BIT(1)
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#define CIR_INTEN_RX_OVF_EN BIT(0)
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#define CIR_INTEN_RX_INT_EN (7)
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#define CIR_TXSTAT_REG 0x0C
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#define CIR_TXSTAT_TX_STA (16)
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#define CIR_TXSTAT_TXFIFO_ERR (10)
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#define CIR_TXSTAT_TXFIFO_FULL (9)
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#define CIR_TXSTAT_TXFIFO_EMPTY (8)
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#define CIR_TXSTAT_TXFIFO_DLEN (0)
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#define CIR_RXSTAT_REG 0x10
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#define CIR_RXSTAT_RX_STA (16)
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#define CIR_RXSTAT_RXFIFO_ERR (10)
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#define CIR_RXSTAT_RXFIFO_FULL (9)
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#define CIR_RXSTAT_RXFIFO_EMPTY BIT(8)
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#define CIR_RXSTAT_RXFIFO_DLEN (0)
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#define CIR_RXCLK_REG 0x14
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#define CIR_RX_THRES_REG 0x18
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#define CIR_RX_THRES_ACTIVE (16)
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#define CIR_RX_THRES_ACTIVE_LEVEL(x) ((x) << CIR_RX_THRES_ACTIVE)
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#define CIR_RX_THRES_IDLE (0)
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#define CIR_RX_THRES_IDLE_LEVEL(x) ((x) << CIR_RX_THRES_IDLE)
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#define CIR_RX_CFG_REG 0x1C
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#define CIR_RX_CFG_NOISE (16)
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#define CIR_RX_CFG_NOISE_LEVEL(x) ((x) << CIR_RX_CFG_NOISE)
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#define CIR_RX_CFG_RX_LEVEL BIT(1)
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#define CIR_RX_CFG_RX_INVERT BIT(0)
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#define CIR_TX_CFG_REG 0x20
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#define CIR_TX_CFG_TX_MODE BIT(2)
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#define CIR_TX_CFG_TX_OUT_MODE BIT(1)
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#define CIR_TX_CFG_TX_INVERT BIT(0)
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#define CIR_TIDC_REG 0x24
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#define CIR_CARR_CFG_REG 0x2C
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#define CIR_CARR_CFG_HIGH (16)
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#define CIR_CARR_CFG_HIGH_VAL(x) ((x) << CIR_CARR_CFG_HIGH)
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#define CIR_CARR_CFG_LOW (0)
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#define CIR_CARR_CFG_LOW_VAL(x) ((x) << CIR_CARR_CFG_LOW)
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#define CIR_RXFIFO_REG 0x30
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#define CIR_TXFIFO_REG 0x80
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#define CIR_VERSION_REG 0xFFC
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typedef enum {
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CIR_EVENT_RECEIVE_COMPLETE,
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CIR_EVENT_ERROR,
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} cir_event_t;
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typedef struct aic_cir_ctrl aic_cir_ctrl_t;
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struct aic_cir_ctrl {
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unsigned long cir_base;
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uint8_t irq_num;
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uint8_t clk_idx;
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void (*callback)(aic_cir_ctrl_t *aic_cir_ctrl, cir_event_t event,
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void *arg);
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void *arg;
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uint8_t tx_data[128];
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uint8_t rx_data[128];
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uint32_t rx_idx;
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uint8_t rx_level;
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uint8_t rx_flag; /* Indicates if rxfifo has received data */
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};
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int hal_cir_init(aic_cir_ctrl_t *aic_cir_ctrl);
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void hal_cir_uninit(aic_cir_ctrl_t *aic_cir_ctrl);
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int hal_cir_set_tx_carrier(aic_cir_ctrl_t * aic_cir_ctrl, uint8_t protocol,
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uint32_t tx_duty);
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void hal_cir_set_rx_sample_clock(aic_cir_ctrl_t * aic_cir_ctrl,
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uint8_t protocol);
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void hal_cir_set_rx_level(aic_cir_ctrl_t * aic_cir_ctrl, uint32_t rx_level);
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void hal_cir_send_data(aic_cir_ctrl_t * aic_cir_ctrl, uint8_t * tx_data,
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uint32_t size);
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void hal_cir_enable_transmitter(aic_cir_ctrl_t * aic_cir_ctrl);
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void hal_cir_disable_transmitter(aic_cir_ctrl_t * aic_cir_ctrl);
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void hal_cir_enable_receiver(aic_cir_ctrl_t * aic_cir_ctrl);
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void hal_cir_disable_receiver(aic_cir_ctrl_t * aic_cir_ctrl);
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irqreturn_t hal_cir_irq(int irq_num, void *arg);
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void hal_cir_attach_callback(aic_cir_ctrl_t * aic_cir_ctrl,
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void *callback, void *arg);
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void hal_cir_detach_callback(aic_cir_ctrl_t * aic_cir_ctrl);
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void hal_cir_rx_reset_status(aic_cir_ctrl_t * aic_cir_ctrl);
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#endif /* _HAL_CIR_H_ */
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