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https://gitee.com/Vancouver2017/luban-lite-t3e-pro.git
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162 lines
5.5 KiB
C
162 lines
5.5 KiB
C
/*
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* Copyright (c) 2022-2024, ArtInChip Technology Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Authors: matteo <duanmt@artinchip.com>
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*/
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#ifndef _ARTINCHIP_HAL_DVP_H_
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#define _ARTINCHIP_HAL_DVP_H_
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#define DVP_PLANE_NUM 2
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#define DVP_MAX_HEIGHT 4096U
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#define DVP_MAX_WIDTH 4096U
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#define DVP_CH_BASE 0x100
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#define DVP_CTL 0x0
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#define DVP_IRQ_EN (DVP_CH_BASE + 0x00)
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#define DVP_IRQ_STA (DVP_CH_BASE + 0x04)
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#define DVP_IRQ_CFG (DVP_CH_BASE + 0x08)
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#define DVP_IN_CFG (DVP_CH_BASE + 0x0C)
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#define DVP_IN_HOR_SIZE (DVP_CH_BASE + 0x10)
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#define DVP_IN_VER_SIZE (DVP_CH_BASE + 0x14)
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#define DVP_OUT_HOR_SIZE (DVP_CH_BASE + 0x20)
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#define DVP_OUT_VER_SIZE (DVP_CH_BASE + 0x28)
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#define DVP_OUT_FRA_NUM (DVP_CH_BASE + 0x30)
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#define DVP_OUT_CUR_FRA (DVP_CH_BASE + 0x34)
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#define DVP_OUT_CTL (DVP_CH_BASE + 0x38)
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#define DVP_OUT_UPDATE_CTL (DVP_CH_BASE + 0x3C)
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#define DVP_OUT_ADDR_BUF0 (DVP_CH_BASE + 0x40)
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#define DVP_OUT_ADDR_BUF1 (DVP_CH_BASE + 0x44)
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#define DVP_OUT_READ_ADDR0 (DVP_CH_BASE + 0x48)
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#define DVP_OUT_READ_ADDR1 (DVP_CH_BASE + 0x4C)
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#define DVP_OUT_LINE_STRIDE0 (DVP_CH_BASE + 0x50)
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#define DVP_OUT_LINE_STRIDE1 (DVP_CH_BASE + 0x54)
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#define DVP_OUT_ADDR_BUF0_SHA (DVP_CH_BASE + 0x58)
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#define DVP_OUT_ADDR_BUF1_SHA (DVP_CH_BASE + 0x5C)
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#define DVP_OUT_LINE_STRIDE_SHA (DVP_CH_BASE + 0x60)
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#define DVP_QOS_CFG (DVP_CH_BASE + 0x2C)
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#define DVP_VER 0xFFC
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#define DVP_CTL_OUT_FMT(v) ((v) << 12)
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#define DVP_CTL_OUT_FMT_MASK GENMASK(14, 12)
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#define DVP_CTL_IN_SEQ(v) ((v) << 8)
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#define DVP_CTL_IN_SEQ_MASK GENMASK(9, 8)
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#define DVP_CTL_IN_FMT(v) ((v) << 4)
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#define DVP_CTL_IN_FMT_MASK GENMASK(6, 4)
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#define DVP_CTL_DROP_FRAME_EN BIT(2)
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#define DVP_CTL_CLR BIT(1)
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#define DVP_CTL_EN BIT(0)
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#define DVP_IRQ_EN_UPDATE_DONE BIT(7)
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#define DVP_IRQ_EN_HNUM BIT(2)
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#define DVP_IRQ_EN_FRAME_DONE BIT(1)
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#define DVP_IRQ_STA_UPDATE_DONE BIT(7)
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#define DVP_IRQ_STA_XY_CODE_ERR BIT(6)
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#define DVP_IRQ_STA_BUF_FULL BIT(3)
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#define DVP_IRQ_STA_HNUM BIT(2)
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#define DVP_IRQ_STA_FRAME_DONE BIT(1)
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#define DVP_IRQ_CFG_HNUM_MASK GENMASK(30, 16)
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#define DVP_IRQ_CFG_HNUM_SHIFT 16
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#define DVP_IN_CFG_FILED_POL_ACTIVE_LOW BIT(3)
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#define DVP_IN_CFG_VSYNC_POL_FALLING BIT(2)
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#define DVP_IN_CFG_HREF_POL_ACTIVE_HIGH BIT(1)
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#define DVP_IN_CFG_PCLK_POL_FALLING BIT(0)
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/* The field definition of IN_HOR_SIZE */
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#define DVP_IN_HOR_SIZE_IN_HOR_MASK GENMASK(30, 16)
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#define DVP_IN_HOR_SIZE_IN_HOR_SHIFT (16)
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#define DVP_IN_HOR_SIZE_XY_CODE_ERR_MASK GENMASK(15, 8)
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#define DVP_IN_HOR_SIZE_XY_CODE_ERR_SHIFT (8)
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#define DVP_IN_HOR_SIZE_XY_CODE_MASK GENMASK(7, 0)
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#define DVP_IN_HOR_SIZE_XY_CODE_SHIFT (0)
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#define DVP_IN_HOR_SIZE_XY_CODE_F BIT(6)
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#define DVP_OUT_HOR_NUM(w) (((w) * 2 - 1) << 16)
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#define DVP_OUT_VER_NUM(h) (((h) - 1) << 16)
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#define DVP_OUT_ADDR_BUF(plane) (plane ? DVP_OUT_ADDR_BUF1 : DVP_OUT_ADDR_BUF0)
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#define DVP_OUT_CTL_CAP_OFF_IMMEDIATELY BIT(1)
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#define DVP_OUT_CTL_CAP_ON BIT(0)
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#define DVP_QOS_CUSTOM BIT(26)
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#define DVP_QOS_INC_THR_MASK GENMASK(25, 17)
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#define DVP_QOS_INC_THR_SHIFT 17
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#define DVP_QOS_DEC_THR_MASK GENMASK(16, 8)
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#define DVP_QOS_DEC_THR_SHIFT 8
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#define DVP_QOS_HIGH_MASK GENMASK(7, 4)
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#define DVP_QOS_HIGH_SHIFT 4
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#define DVP_QOS_LOW_MASK GENMASK(3, 0)
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enum dvp_input {
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DVP_IN_RAW = 0,
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DVP_IN_YUV422 = 1,
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DVP_IN_BT656 = 2,
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};
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enum dvp_output {
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DVP_OUT_RAW_PASSTHROUGH = 0,
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DVP_OUT_YUV422_COMBINED_NV16 = 1,
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DVP_OUT_YUV420_COMBINED_NV12 = 2,
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};
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enum dvp_input_yuv_seq {
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DVP_YUV_DATA_SEQ_YUYV = 0,
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DVP_YUV_DATA_SEQ_YVYU = 1,
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DVP_YUV_DATA_SEQ_UYVY = 2,
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DVP_YUV_DATA_SEQ_VYUY = 3,
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};
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enum dvp_capture_mode {
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DVP_CAPTURE_PICTURE = 0,
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DVP_CAPTURE_VIDEO = 1
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};
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enum dvp_subdev_pads {
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DVP_SUBDEV_SINK = 0,
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DVP_SUBDEV_SOURCE,
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DVP_SUBDEV_PAD_NUM,
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};
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/* Save the configuration information for DVP controller. */
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struct aic_dvp_config {
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/* Input format */
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enum dvp_input input;
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enum dvp_input_yuv_seq input_seq;
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u32 flags;
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u32 interlaced;
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/* Output format */
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enum dvp_output output;
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u32 width;
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u32 height;
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u32 stride[DVP_PLANE_NUM];
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u32 sizeimage[DVP_PLANE_NUM];
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};
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/* Some API of register, Defined in hal_dvp.c */
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void hal_dvp_enable(struct aic_dvp_config *cfg, int enable);
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void hal_dvp_capture_start(void);
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void hal_dvp_capture_stop(void);
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void hal_dvp_clr_fifo(void);
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int hal_dvp_clr_int(void);
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void hal_dvp_enable_int(struct aic_dvp_config *cfg, int enable);
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void hal_dvp_set_pol(u32 flags);
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void hal_dvp_set_cfg(struct aic_dvp_config *cfg);
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void hal_dvp_update_buf_addr(dma_addr_t y, dma_addr_t uv, u32 offset);
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void hal_dvp_update_ctl(void);
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void hal_dvp_record_mode(void);
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void hal_dvp_qos_cfg(u32 high, u32 low, u32 inc_thd, u32 dec_thd);
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u32 hal_dvp_get_current_xy(void);
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u32 hal_dvp_is_top_field(void);
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u32 hal_dvp_is_bottom_field(void);
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void hal_dvp_field_tag_clr(void);
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#endif /* _ARTINCHIP_HAL_DVP_H_ */
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